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Bus encoding for simultaneous delay and energy optimization

Authors:

Jingyi Zhang,

Qing Wu,

Qinru QiuAuthors Info & Claims

ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design

Pages 209 - 212

https://doi.org/10.1145/1393921.1393976

Published: 11 August 2008 Publication History

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Abstract

In this paper we propose two bus encoding algorithms that optimize both bus delay and energy dissipation based on the probabilistic characteristics of data on data buses. The first algorithm minimizes the crosstalk transitions by inserting temporal redundancy and achieves optimal energy. The second algorithm reduces crosstalk more aggressively to achieve optimal bus delay by mapping the original data to low-energy opposite-transition-forbidden codes. Experimental results show that they outperform the existing heuristic bus encoding algorithms by 15.7% to 58.8% in average energy dissipation and 11.4% to 58.4% in average delay.

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Cited By

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Ahmed BSujan Kumar Saha Jiangjiang Liu (2015)Modified bus invert encoding to reduce capacitive crosstalk, power and inductive noise2015 2nd International Conference on Electrical Information and Communication Technologies (EICT)10.1109/EICT.2015.7391929(95-100)Online publication date: Dec-2015
https://doi.org/10.1109/EICT.2015.7391929
Sujan Kumar Saha Ahmed BJiangjiang Liu (2015)A survey on interconnect encoding for reducing power consumption, delay, and crosstalk2015 2nd International Conference on Electrical Information and Communication Technologies (EICT)10.1109/EICT.2015.7391913(7-12)Online publication date: Dec-2015
https://doi.org/10.1109/EICT.2015.7391913
Kornaros G(2010)NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnectsInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2010.0345392:3/4(177-186)Online publication date: 1-Aug-2010
https://dl.acm.org/doi/10.1504/IJHPSA.2010.034539

Index Terms

Bus encoding for simultaneous delay and energy optimization
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Published In

ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design

August 2008

396 pages

ISBN:9781605581095

DOI:10.1145/1393921

General Chairs:
Vijaykrishnan Narayanan
Penn State University
,
C. P. Ravikumar
Texas Instruments
,
Joerg Henkel
Univeristy of Karlsruhe
,
Ali Keshavarzi
Intel Corporation
,
Program Chairs:
Vojin G. Oklobdzija
University of Texas at Dallas
,
Barry Pangrle
Pangrle Consulting

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 11 August 2008

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August 11 - 13, 2008

Bangalore, India

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Ahmed BSujan Kumar Saha Jiangjiang Liu (2015)Modified bus invert encoding to reduce capacitive crosstalk, power and inductive noise2015 2nd International Conference on Electrical Information and Communication Technologies (EICT)10.1109/EICT.2015.7391929(95-100)Online publication date: Dec-2015
https://doi.org/10.1109/EICT.2015.7391929
Sujan Kumar Saha Ahmed BJiangjiang Liu (2015)A survey on interconnect encoding for reducing power consumption, delay, and crosstalk2015 2nd International Conference on Electrical Information and Communication Technologies (EICT)10.1109/EICT.2015.7391913(7-12)Online publication date: Dec-2015
https://doi.org/10.1109/EICT.2015.7391913
Kornaros G(2010)NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnectsInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2010.0345392:3/4(177-186)Online publication date: 1-Aug-2010
https://dl.acm.org/doi/10.1504/IJHPSA.2010.034539

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Serial-link bus: a low-power on-chip bus architecture

A Tour into Ambient Energy Resources and Battery Optimization

Energy Optimization under Informed Mobility

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