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A physical level study and optimization of CAM-based checkpointed register alias table

Published: 11 August 2008 Publication History

Abstract

Using full-custom layouts in 130 nm technology, this work studies how the latency and energy of a checkpointed, CAM-based Register Alias Table (cRAT) vary as a function of the window size, the issue width, and the number of embedded global checkpoints (GCs). These results are compared to those of the SRAM-based RAT (sRAT). Understanding these variations is useful during the early stages of architectural exploration where physical level information is not yet available. It is found that compared to sRAT, cRAT is more sensitive to the number of physical registers and issue width, however, it is less sensitive to the number of GCs. In addition, beyond a certain number of GCs, cRAT becomes faster than its equivalent sRAT. For instance, this is true when a RAT for 64 architectural and 128 physical registers has at least 20 GCs. This work also proposes an energy optimization for the cRAT; this optimization selectively disables cRAT entries that do not result in a match during lookup. The energy savings are, for the most part, a function of the number of physical registers. For instance, for a cRAT with 128 entries energy is reduced by 40%.

References

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Cited By

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  • (2021)VMT: Virtualized Multi-Threading for Accelerating Graph Workloads on Commodity ProcessorsIEEE Transactions on Computers10.1109/TC.2021.3086069(1-1)Online publication date: 2021
  • (2014)Efficient Register Renaming and Recovery for High-Performance ProcessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.227000122:7(1506-1514)Online publication date: Jul-2014
  • (2013)Exploiting replicated checkpoints for soft error detection and correctionProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485642(1494-1497)Online publication date: 18-Mar-2013
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  1. A physical level study and optimization of CAM-based checkpointed register alias table

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        cover image ACM Conferences
        ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design
        August 2008
        396 pages
        ISBN:9781605581095
        DOI:10.1145/1393921
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Publication History

        Published: 11 August 2008

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        Author Tags

        1. checkpointing
        2. energy
        3. latency
        4. register renaming

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        View all
        • (2021)VMT: Virtualized Multi-Threading for Accelerating Graph Workloads on Commodity ProcessorsIEEE Transactions on Computers10.1109/TC.2021.3086069(1-1)Online publication date: 2021
        • (2014)Efficient Register Renaming and Recovery for High-Performance ProcessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.227000122:7(1506-1514)Online publication date: Jul-2014
        • (2013)Exploiting replicated checkpoints for soft error detection and correctionProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485642(1494-1497)Online publication date: 18-Mar-2013
        • (2013)Implementing fast recovery for register alias table in out-of-order processors2013 2nd International Symposium on Instrumentation and Measurement, Sensor Network and Automation (IMSNA)10.1109/IMSNA.2013.6743403(821-824)Online publication date: Dec-2013
        • (2010)On the latency and energy of checkpointed superscalar register alias tablesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201212818:3(365-377)Online publication date: 1-Mar-2010
        • (2009)A power-aware hybrid RAM-CAM renaming mechanism for fast recovery2009 IEEE International Conference on Computer Design10.1109/ICCD.2009.5413160(150-157)Online publication date: Oct-2009

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