research-article

Full-system chip multiprocessor power evaluations using FPGA-based emulation

Authors:

Abhishek Bhattacharjee,

Gilberto Contreras,

Margaret MartonosiAuthors Info & Claims

ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design

Pages 335 - 340

https://doi.org/10.1145/1393921.1394010

Published: 11 August 2008 Publication History

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Abstract

The design process for chip multiprocessors (CMPs) requires extremely long simulation times to explore performance, power, and thermal issues, particularly when operating system (OS) effects are included. In response, our novel FPGA-based emulation methodology models a full CMP design including applications and an OS. Activity counters programmed into the cores feed per-component microarchitectural power models. These models achieve under 10% error compared to detailed gate-level simulations. Our method retains software flexibility, but offers up to 35x speedup compared to corresponding full-system software simulations. We present our approach by emulating a 2-core Leon3 cache-coherent multiprocessor running Linux and parallel benchmarks. In an example case study, our emulated system uses activity counts (a proxy for temperature) to guide process migration between the CMP cores. Overall, this paper's methodology makes possible detailed power and thermal studies of CMPs and their operating systems.

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https://doi.org/10.1109/DCIS58620.2023.10335994
Mettler MRapp MKhdr HMueller-Gritschneder DHenkel JSchlichtmann U(2022)An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core ProcessorsACM Transactions on Architecture and Code Optimization10.1145/351682519:3(1-24)Online publication date: 4-May-2022
https://dl.acm.org/doi/10.1145/3516825
Kim DZhao JBachrach JAsanović K(2019)SimmaniProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358322(1050-1062)Online publication date: 12-Oct-2019
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Full-system chip multiprocessor power evaluations using FPGA-based emulation

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Published In

cover image ACM Conferences

ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design

August 2008

396 pages

ISBN:9781605581095

DOI:10.1145/1393921

General Chairs:
Vijaykrishnan Narayanan
Penn State University
,
C. P. Ravikumar
Texas Instruments
,
Joerg Henkel
Univeristy of Karlsruhe
,
Ali Keshavarzi
Intel Corporation
,
Program Chairs:
Vojin G. Oklobdzija
University of Texas at Dallas
,
Barry Pangrle
Pangrle Consulting

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 11 August 2008

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ISLPED08

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ISLPED08: International Symposium on Low Power Electronics and Design

August 11 - 13, 2008

Bangalore, India

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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https://doi.org/10.1109/DCIS58620.2023.10335994
Mettler MRapp MKhdr HMueller-Gritschneder DHenkel JSchlichtmann U(2022)An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core ProcessorsACM Transactions on Architecture and Code Optimization10.1145/351682519:3(1-24)Online publication date: 4-May-2022
https://dl.acm.org/doi/10.1145/3516825
Kim DZhao JBachrach JAsanović K(2019)SimmaniProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358322(1050-1062)Online publication date: 12-Oct-2019
https://dl.acm.org/doi/10.1145/3352460.3358322
Genser ABachmann CSteger CWeiss RHaid J(2019)A Hardware-Accelerated Estimation-Based Power Profiling Unit - Enabling Early Power-Aware Embedded Software Design and On-Chip Power Management10.1007/978-3-662-58834-5_4(59-78)Online publication date: 23-Feb-2019
https://doi.org/10.1007/978-3-662-58834-5_4
MAYURI CSANJAY AVIJAY C(2017)AN EXPOSITION ON RESCALING OF CACHEi-manager's Journal on Computer Science10.26634/jcom.5.1.137945:1(22)Online publication date: 2017
https://doi.org/10.26634/jcom.5.1.13794
Bjørnseth BDjupdal ANatvig LFanucci LTeich J(2016)A systematic approach to automated construction of power emulation modelsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2971949(600-605)Online publication date: 14-Mar-2016
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Kim DIzraelevitz ACelio CKim HZimmer BLee YBachrach JAsanović K(2016)StroberACM SIGARCH Computer Architecture News10.1145/3007787.300115144:3(128-139)Online publication date: 18-Jun-2016
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Mantovani PCota ETien KPilato CDi Guglielmo GShepard KCarloni L(2016)An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systemsProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897984(1-6)Online publication date: 5-Jun-2016
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Kim DIzraelevitz ACelio CKim HZimmer BLee YBachrach JAsanović KMin SLoh G(2016)StroberProceedings of the 43rd International Symposium on Computer Architecture10.1109/ISCA.2016.21(128-139)Online publication date: 18-Jun-2016
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Najam ZDar MQadri MNajam SAhmed J(2016)Architectural Enhancement of LEON3 Processor for Real Time and Feedback Applications2016 International Conference on Frontiers of Information Technology (FIT)10.1109/FIT.2016.014(29-34)Online publication date: Dec-2016
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