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Instruction-driven clock scheduling with glitch mitigation

Published: 11 August 2008 Publication History

Abstract

Instruction-driven clock scheduling is a mechanism that minimizes clock power in deeply-pipelined datapaths. Analysis of realistic processor workloads shows a preponderance of bubbles persist through pipelines like the floating point unit. Clock scheduling ostensibly adapts pipeline depth with respect to bubbles in the instruction stream without performance loss. Unfortunately, shallower pipelines (i.e. longer pipe stages) are prone to larger amounts of glitches propagating through logic, increasing dynamic power. Experimentally measured results from a 130nm FPU test chip with flexible clocking capabilities show a super-linear increase in glitch-induced dynamic power for shallower pipelines. While higher glitch power can severely diminish the power savings offered by clock scheduling, judicious clocking of intermediate stages offers glitch mitigation to recover power savings for worst-case scenarios. Detailed analysis of clock scheduling applied to a FPU in a POWER4-like processor running realistic workloads shows an average net power savings of 15% compared to an aggressively clock-gated design.

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Cited By

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  • (2015)A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional UnitsIEICE Transactions on Electronics10.1587/transele.E98.C.559E98.C:7(559-568)Online publication date: 2015

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  1. Instruction-driven clock scheduling with glitch mitigation

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    cover image ACM Conferences
    ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design
    August 2008
    396 pages
    ISBN:9781605581095
    DOI:10.1145/1393921
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 11 August 2008

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    Author Tags

    1. clock gating
    2. floating point unit
    3. glitch power
    4. low power

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    • (2015)A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional UnitsIEICE Transactions on Electronics10.1587/transele.E98.C.559E98.C:7(559-568)Online publication date: 2015

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