ABSTRACT
Scaling of transistor feature size over time has been facilitated by corresponding improvement in lithography technology. However, in recent times the wavelength of the optical light source used for photolithography has not scaled in the same rate as that of the minimum feature size of the transistor. In fact, starting with 180nm devices, the wavelength of optical source has remained the same (at 193nm) due to difficulties in finding a flicker-free, high energy, coherent light source with compatible improvement in lens material for focusing this light. Consequently, upcoming technology nodes (65nm, 45nm, 32nm and 22nm) will be using a light source with wavelength much greater than the feature size. This creates a peculiar problem where line width on manufactured devices is a function of relative spacing between adjacent lines. Despite numerous restriction on layout rules, interconnects may still suffer from constriction due to this peculiarity also known as forbidden pitch problem. A small manufacturing variation turns the constrictions to open faults. Gate leakage current is a significant concern for present and upcoming technology nodes. Due to gate leakage, an open fault is not truly an open circuit. Our simulation studies show that the leakage current steers the floating input of a gate to certain meta-stable states. This property actually makes it easier to detect open faults either through side channel excitation or by stuck-at tests. The major contributions of this paper are (i) lithographic simulation based identification of potential open fault sites, (ii) identification of meta-stable input states for these open inputs, (iii) length calculation for side channel signals for definitive detection of open faults. Together, they provide a complete CAD framework for testing lithography related open faults.
- IBS ReportGoogle Scholar
- S. Kundu, A. Sreedhar, and A. Sanyal. "Forbidden pitches in Sub-Wavelength Lithography and their Implications on Design," J. Computer Aided Materials Design, 2007Google ScholarCross Ref
- F. M. Schellenberg. "Resolution enhancement technology: The past, the present and extension for the future," in SPIE Microlithography Symposium, 2004Google Scholar
- Robert Socha, Mircea Dusa, Luigi Capodieci, Jo Finders, Fung Chen, Donis Flagello, Kevin Cummings, "Forbidden pitches for 130nm lithograph and below," Optical Microlithography XIII, Christopher J. Progler, Proceedings of SPIE, Vol. 4000, pp. 1140--1155, 2000.Google Scholar
- A. K. Stamper, T. L. McDevitt, S. L. Luce, "Sub-0.25-micron interconnection scaling: damascene copper versus subtractive aluminum," Proc. Adv. Semiconductor Manufacturing Conference & Workshop, 1998Google Scholar
- Xuelong Shi, Stephen Hsu, Fung Chen, Micheal Hsu, Robert Socha, and Micea Dusa. "Understanding the Forbidden Pitch Phenomenon and Assist Feature Placement," Microlithography XVI, Proc. SPIE Vol. 4689, 2000Google Scholar
- C. A. Mack, "Understanding focus effects in submicron optical lithography," in Optical/Laser Microlithography, Proc. SPIE 922, 135--148 (1988); and Opt. Eng. 27(12), 1093--1100, 1988Google Scholar
- Alfred K Wong et al., "Forbidden area avoidance with spacing technique for layout optimization," Proceedings of SPIE Vol. 5379Google Scholar
- M. Abramovici, M. A. Breuer, and A. D. Friedman. "Digital systems testing and testable design," IEEE Press, Piscataway, NJ, 1990Google Scholar
- K. C. Y. Mei. "Bridging and stuck-at faults," IEEE Trans. Computers, Vol. C-23, pp. 720--727, July 1974 Google ScholarDigital Library
- W. Maly, F. J. Ferguson, and J. P. Shen. "Systematic characterization of physical defects for fault analysis of MOS IC cells," IEEE International Test Conference, pp. 390--399, 1984Google Scholar
- M. Jacomet. "Stuck-at faults vs. layout dependent CMOS faults," IEEE Workshop Defect and Fault Tolerance in VLSI Systems, pp. 62--69, 1990Google Scholar
- C. H. Stapper. "Modeling of integrated circuit defect sensitivities," IBM J. Research and Develeopment, Vol. 27, pp. 549--557, Nov. 1983Google ScholarDigital Library
- M. Jacomet, and W. Guggenbuhl. "Layout-dependent fault analysis and test synthesis for CMOS circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 6, pp. 888--899, June 1993Google ScholarDigital Library
- P. Gupta, and A. B. Kahng. "Manufacturing-aware physical design," IEEE International Conf. Computer Aided Design, pp. 681--687, Nov. 2003 Google ScholarDigital Library
- W. Maly, "A DRC-Based Algorithm for Extraction of Critical Areas for Opens in Large VLSI Circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 1999Google Scholar
- J. A. Roy et. al, "Capo: Robust and Scalable Open-Source Min-cut Floorplacer," Proc. Intl. Symposium on Physical Design (ISPD 2005) Google ScholarDigital Library
- H. Konuk, F. J. Ferguson, and T. Larrabee. "Charge-based fault simulation for CMOS network breaks," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 12, pp. 1555--1567, 1996 Google ScholarDigital Library
- D. G. Saab, Y. G. Saab, and J. A. Abraham. "CRIS: a test cultivation program for sequential VLSI circuits," IEEE/ACM International Conference on Computer Aided Design, pp. 216--219, 1992 Google ScholarDigital Library
Index Terms
- On modeling and testing of lithography related open faults in nano-CMOS circuits
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