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Multilayer stacking technology using wafer-to-wafer stacked method

Published: 07 November 2008 Publication History

Abstract

We have developed a new three-dimensional stacking technology using the wafer-to-wafer stacked method. Electrical conductivity between each wafer is almost 100% and contact resistance is less than 0.7Ω between a through-silicon via (TSV) and a microbump. We have also created a prototype of a three-layer stacking device using our technology, where each wafer for the stacking is fabricated by using 0.18um CMOS technology based on 8-inch wafers. The device is operated by two times the frequency of the multichip module (MCM) device case using a two-dimensional device with identical functions and minimally different power consumption. The yields obtained from the results comprising all functional tests are over 60%.

References

[1]
Fukushima, T., Yamada, Y., Kikuchi, H., and Koyanagi, M. 2005. New three-dimensional integration technology using self-assembly technique. In IEEE International Electronic Devices Meeting Conference Digest Technology Papers, 359--362.
[2]
ISSCC. 2007. ISSCC Forum on the Design of 3D-Chipstacks.
[3]
Iwata, A., Sasaki, M., Kikkawa, T., Kameda, S., Ando, H., Kimoto, D., Arizono, D., and Sunami, H. 2005. A 3D integration scheme utilizing wireless interconnections for implementing hyper brains. ISSCC Dig. Tech. Papers, 262--263.
[4]
Koyanagi, M., Kurino, H., Lee, K. W., Sakuma, K., Miyakawa, N., and Itani, H. C. 1998. Future system-on-silicon LSI chips. IEEE Micro. 18, 4, 17--22.
[5]
Maebashi, T., Nakamura, N., Nakayama, N., and Miyakawa, N. 2007. New fabrication method for multi-layer stacked devices using wafer-to-wafer stacked technology based on 8-inch wafers.ESSDERC, 251--254.
[6]
Morrow, P. R., Park, C.-M., Ramanathan, S., Kobrisksy, M. J., and Harmes, M. 2006. Three-Dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/Low-k. IEEE Electron. Devices 27, 5 (May).
[7]
RTI. 2004--2007. Proceedings of the 3D Architectures for Semiconductor Integration and Packaging Conference.
[8]
Schaper, L. 2004. Copper electroplated through silicon vias for 3-DIC interconnection. In Proceedings of Advanced Metallization Conference, MINI-Workshop.
[9]
SEMANTIC. 2004. Proceedings of the 3D Technology, Modeling, and Process Symposium.
[10]
Topol, A. W., La Tulipe, D. C., Shi, L., Alam, S. M., Frank, D. J., Steen, S. E., Vichiconti, J., Posillico, D., Cobb, M., Medd, S., Patel, J., Goma, S., DiMilia, D., Robson, M. T., Duch, E., Farinelli, M, Wang, C., Conti, R. A., Canaperi, L., Deligianni, A., Kummar, A., Kwietniak, K. T., D'emic, C., Ott, J., Young, A. M., Guarini, K. W., and Leong, M. 2005. Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs). In IEEE International Electronic Devices Meeting Conference Digest Technology Papers, 363--366.
[11]
Xie, Y., Loh, G., Black, B., and Bernstein, K. 2006. Design space exploration for 3D architectures. ACM J. Emerg. Technol. Comput. Syst. 2, 65--103.

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  • (2022)Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)Electronics10.3390/electronics1102023611:2(236)Online publication date: 12-Jan-2022
  • (2020)Scalable Design Methodology and Online Algorithm for TSV-Cluster Defects Recovery in Highly Reliable 3D-NoC SystemsIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2017.27624078:3(577-590)Online publication date: 1-Jul-2020
  • (2018)Cu diffusion into the glass under bias temperature stress condition for through glass vias (TGV) applicationsInternational Symposium on Microelectronics10.4071/2380-4505-2018.1.0002592018:1(000259-000263)Online publication date: Oct-2018
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cover image ACM Journal on Emerging Technologies in Computing Systems
ACM Journal on Emerging Technologies in Computing Systems  Volume 4, Issue 4
October 2008
123 pages
ISSN:1550-4832
EISSN:1550-4840
DOI:10.1145/1412587
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 07 November 2008
Accepted: 01 July 2008
Received: 01 June 2008
Published in JETC Volume 4, Issue 4

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Author Tags

  1. 3D integration
  2. design
  3. hardware
  4. stacking process

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Cited By

View all
  • (2022)Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)Electronics10.3390/electronics1102023611:2(236)Online publication date: 12-Jan-2022
  • (2020)Scalable Design Methodology and Online Algorithm for TSV-Cluster Defects Recovery in Highly Reliable 3D-NoC SystemsIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2017.27624078:3(577-590)Online publication date: 1-Jul-2020
  • (2018)Cu diffusion into the glass under bias temperature stress condition for through glass vias (TGV) applicationsInternational Symposium on Microelectronics10.4071/2380-4505-2018.1.0002592018:1(000259-000263)Online publication date: Oct-2018
  • (2017)A Cost-Effective Fault Tolerance Technique for Functional TSV in 3-D ICsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.268170325:7(2071-2080)Online publication date: Jul-2017
  • (2016)Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2016.7753572(1-6)Online publication date: Sep-2016
  • (2015)Online Fault Tolerance Technique for TSV-Based 3-D-ICIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.234315623:8(1567-1571)Online publication date: Aug-2015
  • (2015)Integration of CNTs in 3D-IC interconnects: a non-destructive approach for the precise characterization and elucidation of interfacial propertiesJournal of Materials Chemistry A10.1039/C4TA04715J3:5(2082-2089)Online publication date: 2015
  • (2013)High-Efficient Chip to Wafer Self-Alignment and Bonding Applicable to MEMS-IC Flexible IntegrationIEEE Sensors Journal10.1109/JSEN.2012.222542213:2(651-656)Online publication date: Feb-2013
  • (2013)Distortion-free stacked CMOS image sensor with 8.6-μm pitch micro-bump interconnections2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS)10.1109/EDAPS.2013.6724442(1-4)Online publication date: Dec-2013
  • (2013)Size-free MEMS-IC high-efficient integration by using carrier wafer with self-assembled monolayer (SAM) fine pattern2013 IEEE 63rd Electronic Components and Technology Conference10.1109/ECTC.2013.6575771(1508-1513)Online publication date: May-2013
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