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Data path issues in a highly concurrent machine
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Source International Symposium on Microarchitecture archive
Proceedings of the 25th annual international symposium on Microarchitecture table of contents
Portland, Oregon, United States
Pages: 115 - 118  
Year of Publication: 1992
ISBN:0-8186-3175-9
Also published in ...
Authors
Augustus K. Uht
Darin B. Johnson
Sponsors
IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 8,   Citation Count: 2
Additional Information:

references   cited by   index terms   collaborative colleagues   peer to peer  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Kai Hwang , Faye A. Briggs, Computer Architecture and Parallel Processing, McGraw-Hill, Inc., New York, NY, 1990
 
2
Augustus Kinzel Uht, Hardware extraction of low-level concurrency from sequential instruction streams (parallelism, implementation, architecture, dependencies, semantics), 1985
 
3
Augustus K. Uht, A Theory of Reduced and Minimal Procedural Dependencies, IEEE Transactions on Computers, v.40 n.6, p.681-692, June 1991  [doi>10.1109/12.90247 ]
 
4
Augustus K. Uht, Concurrency Extraction Via Hardware Methods Executing the Static Instruction Stream, IEEE Transactions on Computers, v.41 n.7, p.826-841, July 1992  [doi>10.1109/12.256451 ]
 
5
Uht, A. K. and Johnson, D. B. Data Path Issues in a Highly Concurrent Machine. Technical Report CS92-262, Deparunent of Computer Science and Engineering, University of California, San Diego, September, 1992.
 
6
Wedig, R. G. Detection of Concurrency in Directly Executed Language Instruction Streams. PhD thesis, Stanford University, June, 1982.

CITED BY  2
 
Augustus K. Uht , Vijay Sindagi , Kelley Hall, Disjoint eager execution: an optimal form of speculative execution, Proceedings of the 28th annual international symposium on Microarchitecture, p.313-325, November 29-December 01, 1995, Ann Arbor, Michigan, United States
 
Luis A. Lozano , Guang R. Gao, Exploiting short-lived variables in superscalar processors, Proceedings of the 28th annual international symposium on Microarchitecture, p.292-302, November 29-December 01, 1995, Ann Arbor, Michigan, United States

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Parallel processors**

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Data-path design

  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Instruction set design (e.g., RISC, CISC, VLIW)


General Terms:
Design, Performance

Collaborative Colleagues:
Augustus K. Uht: colleagues
Darin B. Johnson: colleagues

Peer to Peer - Readers of this Article have also read:
This Article has also been published in:

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