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Tradeoffs in processor/memory interfaces for superscalar processors
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Source International Symposium on Microarchitecture archive
Proceedings of the 25th annual international symposium on Microarchitecture table of contents
Portland, Oregon, United States
Pages: 202 - 205  
Year of Publication: 1992
ISBN:0-8186-3175-9
Also published in ...
Author
Thomas M. Conte
Sponsors
IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
Bibliometrics
Downloads (6 Weeks): 0,   Downloads (12 Months): 8,   Citation Count: 4
Additional Information:

references   cited by   index terms   collaborative colleagues   peer to peer  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
W. M. Johnson, Super-scalar processor design, Stanford University, Stanford, CA, 1990
 
2
David Kroft, Lockup-free instruction fetch/prefetch cache organization, Proceedings of the 8th annual symposium on Computer Architecture, p.81-87, May 12-14, 1981, Minneapolis, Minnesota, United States
3
Gurindar S. Sohi , Manoj Franklin, High-bandwidth data memory systems for superscalar processors, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.53-62, April 08-11, 1991, Santa Clara, California, United States
 
4
"Spec newsletter," Feb. 1989. SPEC, Fremont, CA.
 
5
Thomas Martin Conte, Systematic computer architecture prototyping, University of Illinois at Urbana-Champaign, Champaign, IL, 1992

CITED BY  4
 
Soo-Mook Moon, Increasing cache bandwidth using multi-port caches for exploiting ILP in non-numerical code, Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, p.294-297, June 27-29, 1995, Limassol, Cyprus
Kenneth M. Wilson , Kunle Olukotun , Mendel Rosenblum, Increasing cache port efficiency for dynamic superscalar microprocessors, ACM SIGARCH Computer Architecture News, v.24 n.2, p.147-157, May 1996
Kenneth M. Wilson , Kunle Olukotun, Designing high bandwidth on-chip caches, ACM SIGARCH Computer Architecture News, v.25 n.2, p.121-132, May 1997
 
Andrew Wolfe , Rodney Boleyn, Two-ported cache alternatives for superscalar processors, Proceedings of the 26th annual international symposium on Microarchitecture, p.41-48, December 01-03, 1993, Austin, Texas, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.1 CONTROL STRUCTURES AND MICROPROGRAMMING

Additional Classification:
  B. Hardware
  B.1 CONTROL STRUCTURES AND MICROPROGRAMMING
      B.1.5 Microcode Applications
          Subjects: Instruction set interpretation
  B.2 ARITHMETIC AND LOGIC STRUCTURES
      B.2.1 Design Styles
          Subjects: Parallel
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories


General Terms:
Design, Performance

Collaborative Colleagues:
Thomas M. Conte: colleagues

Peer to Peer - Readers of this Article have also read:
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