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Control flow optimization in loops using interval analysis

Published: 19 October 2008 Publication History

Abstract

We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for significant performance increase. The transformation technique optimizes loops containing nested conditional blocks. Specifically, the transformation takes advantage of the fact that the Boolean value of the conditional expression, determining the true/false paths, can be statically analyzed using a novel interval analysis technique that can evaluate conditional expressions in the general polynomial form. Results from interval analysis combined with loop dependency information is used to partition the iteration space of the nested loop. In such cases, the loop nest is decomposed such as to eliminate the conditional test, thus substantially reducing the execution time. Our technique completely eliminates the conditional from the loops (unlike previous techniques) thus further facilitating the application of other optimizations and improving the overall speedup. Applying the proposed transformation technique on loop kernels taken from Mediabench, SPEC-2000, mpeg4, qsdpcm and gimp, on average we measured a 175% (1.75X) improvement of execution time when running on a SPARC processor, a 336% (4.36X) improvement of execution time when running on an Intel Core Duo processor and a 198.9% (2.98X) improvement of execution time when running on a PowerPC G5 processor.

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Cited By

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  • (2024)CoSense: Compiler Optimizations using Sensor Technical SpecificationsProceedings of the 33rd ACM SIGPLAN International Conference on Compiler Construction10.1145/3640537.3641576(73-85)Online publication date: 17-Feb-2024
  • (2013)Mis-speculation-Driven Compiler Framework for Aggressive Loop Automatic ParallelizationProceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum10.1109/IPDPSW.2013.165(1159-1168)Online publication date: 20-May-2013
  • (2009)Efficient dynamic voltage/frequency scaling through algorithmic loop transformationProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629464(203-210)Online publication date: 11-Oct-2009

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cover image ACM Conferences
CASES '08: Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
October 2008
274 pages
ISBN:9781605584690
DOI:10.1145/1450095
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 October 2008

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Author Tags

  1. algorithmic code transformation
  2. compiler loop optimization
  3. interval analysis

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ESWEEK 08
ESWEEK 08: Fourth Embedded Systems Week
October 19 - 24, 2008
GA, Atlanta, USA

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Overall Acceptance Rate 52 of 230 submissions, 23%

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Cited By

View all
  • (2024)CoSense: Compiler Optimizations using Sensor Technical SpecificationsProceedings of the 33rd ACM SIGPLAN International Conference on Compiler Construction10.1145/3640537.3641576(73-85)Online publication date: 17-Feb-2024
  • (2013)Mis-speculation-Driven Compiler Framework for Aggressive Loop Automatic ParallelizationProceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum10.1109/IPDPSW.2013.165(1159-1168)Online publication date: 20-May-2013
  • (2009)Efficient dynamic voltage/frequency scaling through algorithmic loop transformationProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629464(203-210)Online publication date: 11-Oct-2009

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