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Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing

Published: 01 January 2009 Publication History

Abstract

Runtime Reconfiguration (RTR) has been traditionally utilized as a means for exploiting the flexibility of High-Performance Reconfigurable Computers (HPRCs). However, the RTR feature comes with the cost of high configuration overhead which might negatively impact the overall performance. Currently, modern FPGAs have more advanced mechanisms for reducing the configuration overheads, particularly Partial Runtime Reconfiguration (PRTR). It has been perceived that PRTR on HPRC systems can be the trend for improving the performance. In this work, we will investigate the potential of PRTR on HPRC by formally analyzing the execution model and experimentally verifying our analytical findings by enabling PRTR for the first time, to the best of our knowledge, on one of the current HPRC systems, Cray XD1. Our approach is general and can be applied to any of the available HPRC systems. The paper will conclude with recommendations and conditions, based on our conceptual and experimental work, for the optimal utilization of PRTR as well as possible future usage in HPRC.

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        cover image ACM Transactions on Reconfigurable Technology and Systems
        ACM Transactions on Reconfigurable Technology and Systems  Volume 1, Issue 4
        January 2009
        161 pages
        ISSN:1936-7406
        EISSN:1936-7414
        DOI:10.1145/1462586
        Issue’s Table of Contents
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Publication History

        Published: 01 January 2009
        Accepted: 01 October 2008
        Revised: 01 October 2008
        Received: 01 April 2008
        Published in TRETS Volume 1, Issue 4

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        Author Tags

        1. High performance computing
        2. dynamic partial reconfiguration
        3. field programmable gate arrays (FPGA)
        4. reconfigurable computing

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        • (2017)Virtualized Execution Runtime for FPGA Accelerators in the CloudIEEE Access10.1109/ACCESS.2017.26615825(1900-1910)Online publication date: 2017
        • (2017)Run-time management of systems with partially reconfigurable FPGAsIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00857:C(34-44)Online publication date: 1-Mar-2017
        • (2016)Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.241759524:2(530-543)Online publication date: Feb-2016
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