research-article

Temperature-aware register reallocation for register file power-density minimization

Authors:

Xiangrong Zhou,

Peter PetrovAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 14, Issue 2

Article No.: 26, Pages 1 - 22

https://doi.org/10.1145/1497561.1497569

Published: 07 April 2009 Publication History

Abstract

Increased chip temperature has been known to cause severe reliability problems and to significantly increase leakage power. The register file has been previously shown to exhibit the highest temperature compared to all other hardware components in a modern high-end embedded processor, which makes it particularly susceptible to faults and elevated leakage power. We show that this is mostly due to the highly clustered register file accesses where a set of few registers physically placed close to each other are accessed with very high frequency. We propose compile-time temperature-aware register reallocation methodologies for breaking such groups of registers and to uniformly distribute the accesses to the register file. This is achieved with no performance and no hardware overheads. We show that the underlying problem is NP-hard, and subsequently introduce and evaluate two efficient algorithmic heuristics. Our extensive experimental study demonstrates the efficiency of the proposed methodology.

References

[1]

Agrawal, B. and Sherwood, T. 2006. Guiding architectural sram models. In Proceedings of the International Conference on Computer Design (ICCD).

[2]

Amrutur, B. and Horowitz, M. 2000. Speed and power scaling of sram's. IEEE J. Solid-State Circ. 35, 2, 175--185.

[3]

Atienza, D., Raghavan, P., Ayala, J., Micheli, G. D., Catthoor, F., Verkest, D., and Lopez-Vallejo, M. 2006. Compiler-driven leakage energy reduction in banked register files. Lecture Notes in Computer Science, vol 4148, 107--116.

Digital Library

[4]

Babel, L., Kellerer, H., and Kotov, V. 1998. The k-partitioning problem. Math. Meth. Op. Resea. 47, 1, 59--82.

[5]

Brooks, D. and Martonosi, M. 2001. Dynamic thermal management for high-performance microprocessors. In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA). 171--182.

Digital Library

[6]

Coffman, E. G. 1976. Computer and Job-Shop Scheduling Theory. John Wiley & Sons Inc.

[7]

Donald, J. and Martonosi, M. 2006. Techniques for multicore thermal management: Classification and new exploration. In Prcoceedings of the International Symposium on Computer Architecture (ISCA). 78--88.

Digital Library

[8]

Fisher, J., Faraboschi, P., and Young, C. 2005. Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools. Morgan Kaufmann.

[9]

Gunther, S., Binns, F., Carmean, D., and Hall, J. 2001. Managing the impact of increasing microprocessor power consumption. Intel Techn. J.

[10]

Guthaus, M., Ringenberg, J. S., Ernst, D., Austin, T., Mudge, T., and Brown, R. 2001. Mibench: A free, commercially representative embedded benchmark suite. In Workshop on Workload Characterization (WWC-4). 3--14.

Digital Library

[11]

Heo, S., Barr, K., and Asanovic, K. 2003. Reducing power density through activity migration. In Proceedings of the International Symposium on Low-Power Electronics and Design. 217--222.

Digital Library

[12]

Kandemir, M., Vijaykrishnan, N., Irwin, M., Ye, W., and Demirkiran, I. 2000. Register relabeling: A post compilation technique for energy reduction. In Proceedings of the Workshop on Compilers and Operating Systems for Low Power (COLP).

[13]

Ku, J., Ozdemir, S., Memik, G., and Ismail, Y. 2005. Thermal management of on-chip caches through power density minimization. In Proceedings of the International Symposium on Microarchitecture (MICRO). 283--293.

Digital Library

[14]

Kursun, E., Cher, C., Buyuktosunoglu, A., and Bose, P. 2006. Investigating the effects of task scheduling on thermal behavior. In Proceedings of the Workshop on Temperature-Aware Computer Systems (TACS).

[15]

Lee, C., Potkonjak, M., and Mangione-Smith, W. H. 1997. Mediabench: A tool for evaluating and synthesizing multimedia and communications systems. In Proceedings of the International Symposium on Microarchitecture (MICRO). 330--335.

Digital Library

[16]

Li, P., Deng, Y., and Pileggi, L. T. 2005. Temperature-dependent optimization of cache leakage power dissipation. In Proceedings of the International Conference on Computer Design (ICCD). 7--12.

Digital Library

[17]

Mahajan, R. 2002. Thermal management of cpus: A perspective on trends, needs and opportunities. In Proceedings of THERMINIC-8.

[18]

Mehta, H., Owens, R. M., Irwin, M. J., Chen, R., and Ghosh, D. 1997. Techniques for low energy software. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED). 72--75.

Digital Library

[19]

Mukherjee, R. and Memik, S. 2006. Systematic temperature sensor allocation and placement for microprocessors. In Proceedings of the Design Automation Conference (DAC). 542--547.

Digital Library

[20]

Narayanan, S., Kandemir, M., and Ozturk, O. 2006. Compiler-directed power density reduction in noc-based multi-core designs. In Proceedings of the Iinternational Symposium on Quality Electronics Design. 570--575.

Digital Library

[21]

Patel, K., Lee, W., and Pedram, M. 2007. Active bank switching for temperature control of the register file in a microprocessor. In Proceedings of the Great Lakes Symposium on VLSI Systems (GLSVLSI). 231--234.

Digital Library

[22]

Skadron, K., Stan, M., Huang, W., Velusamy, S., Sankaranarayanan, K., and Tarjan, D. 2003. Temperature-aware computer systems: Opportunities and challenges. IEEE Micro 23, 6, 52--61.

Digital Library

[23]

Srinivasan, J. and Adve, S. 2003. Predictive dynamic thermal management for multimedia applications. In Proceedings of the International Conference on Supercomputering (ICS). 109--120.

Digital Library

[24]

Tarjan, D., Thoziyoor, S., and Jouppi, N. 2006. Cacti 4.0: An integrated cache timing, power and area model. Tech. rep., HP Laboratories Palo Alto.

[25]

Ye, W., Vijaykrishnan, N., Kandemir, M., and Irwin, M. J. 2000. The design and use of simplepower: a cycle-accurate energy estimation tool. In Proceedings of the Design Automation Conference (DAC). 340--345.

Digital Library

[26]

Yeh, L. and Chu, R. 2001. Thermal Management of Microelectronic Equipment. American Society of Mechanical Engineers.

[27]

Zhang, Y. 2003. Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects. Tech. rep., CS-2003-05, University of Virginia.

Cited By

Díaz Álvarez JRisco-Martín JColmenar J(2018)Evolutionary design of the memory subsystemApplied Soft Computing10.1016/j.asoc.2017.09.04762(1088-1101)Online publication date: Jan-2018
https://doi.org/10.1016/j.asoc.2017.09.047
Ahmed FSabry MAtienza DMilor L(2012)Wearout-aware compiler-directed register assignment for embedded systemsThirteenth International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2012.6187471(33-40)Online publication date: Mar-2012
https://doi.org/10.1109/ISQED.2012.6187471
Hsu CChen SYang C(2011)Dynamic Voltage Adjustment for Energy Efficient Scheduling on Multi-core SystemsProceedings of the 2011 IEEE Ninth International Symposium on Parallel and Distributed Processing with Applications Workshops10.1109/ISPAW.2011.73(197-202)Online publication date: 26-May-2011
https://dl.acm.org/doi/10.1109/ISPAW.2011.73
Show More Cited By

Index Terms

Temperature-aware register reallocation for register file power-density minimization
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems
2. Software and its engineering
  1. Software notations and tools
    1. Compilers

Recommendations

Register file partitioning and recompilation for register file power reduction

Register files in modern embedded processors contribute a substantial budget in the energy consumption due to their large switching capacitance and long working time. For some embedded processors, on average 25% of registers account for 83% of register ...
Bypass aware instruction scheduling for register file power reduction
Proceedings of the 2006 LCTES Conference

Since register files suffer from some of the highest power densities within processors, designers have investigated several architectural strategies for register file power reduction, including "On Demand RF Read" where the register file is read only if ...
Multiple-banked register file architectures
Special Issue: Proceedings of the 27th annual international symposium on Computer architecture (ISCA '00)

The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor generations, as they are expected to increase the issue width (which implies ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 14, Issue 2

March 2009

384 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1497561

Issue’s Table of Contents

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 07 April 2009

Accepted: 01 December 2008

Revised: 01 August 2008

Received: 01 April 2008

Published in TODAES Volume 14, Issue 2

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Research-article
Research
Refereed

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
299
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 08 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Díaz Álvarez JRisco-Martín JColmenar J(2018)Evolutionary design of the memory subsystemApplied Soft Computing10.1016/j.asoc.2017.09.04762(1088-1101)Online publication date: Jan-2018
https://doi.org/10.1016/j.asoc.2017.09.047
Ahmed FSabry MAtienza DMilor L(2012)Wearout-aware compiler-directed register assignment for embedded systemsThirteenth International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2012.6187471(33-40)Online publication date: Mar-2012
https://doi.org/10.1109/ISQED.2012.6187471
Hsu CChen SYang C(2011)Dynamic Voltage Adjustment for Energy Efficient Scheduling on Multi-core SystemsProceedings of the 2011 IEEE Ninth International Symposium on Parallel and Distributed Processing with Applications Workshops10.1109/ISPAW.2011.73(197-202)Online publication date: 26-May-2011
https://dl.acm.org/doi/10.1109/ISPAW.2011.73
Sabry MAyala JAtienza DBahar RLombardi FAtienza DBrunvand E(2010)Thermal-aware compilation for system-on-chip processing architecturesProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785535(221-226)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785535
Sabry MAyala JAtienza D(2010)Thermal-Aware Compilation for Register Window-Based Embedded ProcessorsIEEE Embedded Systems Letters10.1109/LES.2010.20813432:4(103-106)Online publication date: 1-Dec-2010
https://dl.acm.org/doi/10.1109/LES.2010.2081343

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Issue’s Table of Contents