High-performance, high-capacity single-chip microcomputers
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Time-division-multiplexed arbitration in silicon nanophotonic networks-on-chip for high-performance chip multiprocessors
As the computational performance of microprocessors continues to grow through the integration of an increasing number of processing cores on a single die, the interconnection network has become the central subsystem for providing the communications ...
Dynamically configurable bus topologies for high-performance on-chip communication
The on-chip communication architecture is a primary determinant of overall performance in complex system-on-chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that ...
A high-performance low-power nanophotonic on-chip network
ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and designOn-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfer, limits the power efficiency and performance scalability of many-core chip-...
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- AFIPS: American Federation of Information Processing Societies
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Association for Computing Machinery
New York, NY, United States
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