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MPP: a supersystem for satellite image processing

Published: 07 June 1982 Publication History

Abstract

In 1971 NASA Goddard Space Flight Center initiated a program to develop high-speed image processing systems. These systems use thousands of processing elements (PE's) operating simultaneously to achieve their speed (massive parallelism). A typical satellite image contains millions of picture elements (pixels) that can generally be processed in parallel. In 1979 a contract was awarded to construct a massively parallel processor (MPP) to be delivered in 1982. The processor has 16,896 PE's arranged in a 128-row by 132-column rectangular array. The PE's are in the array unit (Figure 1). Other major blocks in the massively parallel processor are the array control unit, the staging memory, the program and data management unit, and the interface to a host computer.

References

[1]
Siegel, H. J., and S. D. Smith, "Study of Multistage SIMD Interconnection Networks," Proceedings of the 5th Annual Symposium on Computer Architecture, Palo Alto, Calif., April 1978. IEEE Computer Society, Long Beach, Calif., pp. 223--229.
[2]
Fung, L. W., "A Massively Parallel Processing Computer," in High-Speed Computer and Algorithm Organization, D. J. Kuck et al. eds., New York: Academic Press, 1977, pp. 203--204.
[3]
Fung, L. W., "MPPC: A Massively Parallel Processing Computer," GSFC Image Systems Section Report, Sept. 1976, Goddard Space Flight Center, Green-belt, MD.
[4]
Batcher, K. E. "The Multidimensional Access Memory in STARAN." IEEE Transactions on Computers, C-26 (1977), pp. 174--177

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AFIPS '82: Proceedings of the June 7-10, 1982, national computer conference
June 1982
857 pages
ISBN:088283035X
DOI:10.1145/1500774
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Association for Computing Machinery

New York, NY, United States

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Published: 07 June 1982

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