Clock power reduction for virtex-5 FPGAs

ABSTRACT

Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx Virtex-5 FPGA are presented. The approaches are unique in that they leverage specific architectural aspects of Virtex-5 to achieve reductions in dynamic power consumed by the clock network. The first approach comprises a placement-based technique to reduce interconnect resource usage on the clock network, thereby reducing capacitance and power (up to 12%). The second approach borrows the "clock gating" notion from the ASIC domain and applies it to FPGAs. Clock enable signals on flip-flops are selectively migrated to use the dedicated clock enable available on the FPGA's built-in clock network, leading to reduced toggling on the clock interconnect and lower power (up to 28%). Power reductions are achieved without any performance penalty, on average.

References

1. Actel, Corp., Mountain View, CA. IGLOO Low-Power Flash FPGAs General Description, 2007.
2. T. Ahmed, P. Kundarewich, J. Anderson, B. Taylor, and R Aggarwal. Architecture-specific packing for Virtex-5 FPGAs. In ACM/SIGDA Int'l Symposium on Field Programmable Gate Arrays, pages 5--13, Monterey, CA, 2008.
3. Altera, Corp., San Jose, CA. Stratix-III FPGA Family Data Sheet, 2008.
4. J.H. Anderson and F.N. Najm. Low-power programmable FPGA routing circuitry. In IEEE/ACM International Conference on Computer-Aided Design, pages 602--609, San Jose, CA, 2004.
5. J.H. Anderson, F.N. Najm, and T. Tuan. Active leakage power optimization for FPGAs. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 33--41, Monterey, CA, 2004.
6. I. Brynjolfson and Z. Zilic. Dynamic clock management for low power applications in FPGAs. In IEEE Custom Integrated Circuits Conference, pages 139--142, Orlando, FL, 2000.
7. B.H. Calhoun, F.A. Honore, and A. Chandrakasan. Design methodology for fine-grained leakage control in MTCMOS. In ACM/IEEE International Symposium on Low-Power Electronics and Design, pages 104--109, Seoul, Korea, 2003.
8. D. Chen and J. Cong. Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. In ACM/IEEE International Symposium on Low-Power Electronics and Design, pages 70--73, Newport Beach, CA, 2004.
9. D. Chen, J. Cong, and Y. Fan. Low-power high-level synthesis for FPGA architectures. In ACM/IEEE International Symposium on Low-Power Electronics and Design, pages 134--139, Seoul, Korea, 2003.
10. D. Chen, J. Cong, Y Fan, and Z. Zhang. High-level power estimation and low-power design space exploration for FPGAs. In IEEE/ACM Asia and South Pacific Design Automation Conference, pages 529--534, Yokohama, Japan, 2007.
11. L. Ciccarelli, A. Lodi, and R. Canegallo. Low leakage circuit design for FPGAs. In IEEE Custom Integrated Circuits Conference, pages 715--718, Orlando, FL, 2004.
12. M. Donno, A. Ivaldi, L. Benini, and E. Macii. Clock-tree power optimization based on RTL clock-gating. In IEEE/ACM Design Automation Conference, pages 622--627, Anaheim, CA, 2003.
13. A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M.J. Irwin, and T. Tuan. Reducing leakage energy in FPGAs using region-constrained placement. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 51--58, Monterey, CA, 2004.
14. S. Gupta, J. Anderson, L. Farragher, and Q. Wang. CAD techniques for power optimization in Virtex-5 FPGAs. In IEEE Custom Integrated Circuits Conference, pages 85--88, San Jose, CA, 2007.
15. I. Kuon and J. Rose. Measuring the gap between FPGAs and ASICs. IEEE Trans. On CAD of Integrated Circuits and Systems, 26(2):203--215, February 2007.
16. J. Lamoureux, G. Lemieux, and S. Wilton. GlitchLess: an active glitch minimization technique in FPGAs. In ACM/SIGDA Int'l Symposium on Field Programmable Gate Arrays, pages 156--165, Monterey, CA, 2007.
17. J. Lamoureux and S.J.E. Wilton. On the interaction between power-aware FPGA CAD algorithms. In IEEE/ACM International Conference on Computer-Aided Design, pages 701--708, San Jose, CA, 2003.
18. J. Lamoureux and S.J.E. Wilton. FPGA clock network architecture: flexibility vs. area and power. In ACM/SIGDA Int'l Symposium on Field Programmable Gate Arrays, pages 101--108, Monterey, CA, 2006.
19. J. Lamoureux and S.J.E. Wilton. Clock-aware placement for FPGAs. In IEEE International Conference on Field-Programmable Logic and Applications, pages 124--131, Amsterdam, The Netherlands, 2007.
20. F. Li, D. Chen, L. He, and J. Cong. Architecture evaluation for power-efficient FPGAs. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 175--184, Monterey, CA, 2003.
21. F. Li and L.He. Vdd programmability to reduce FPGA interconnect power. In IEEE/ACM International Conference on Computer-Aided Design, pages 760--765, San Jose, CA, 2004.
22. F. Li, Y. Lin, and L. He. FPGA power reduction using configurable dual-Vdd. In ACM/IEEE Design Automation Conference, pages 735--740, San Diego, CA, 2004.
23. A. Rahman and V. Polavarapuv. Evaluation of low-leakage design techniques for field-programmable gate arrays. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 23--30, Monterey, CA, 2004.
24. K. Roy. Power-dissipation driven FPGA place and route under timing constraints. IEEE Transactions On Circuits and Systems, 46(5):634--637, May 1999.
25. L. Shang, A. Kaviani, and K. Bathala. Dynamic power consumption in the Virtex-II FPGA family. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 157--164, Monterey, CA, 2002.
26. A. Singh and M. Marek-Sadowska. Efficient circuit clustering for area and power reduction in FPGAs. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 59--66, Monterey, CA, February 2002.
27. R. Tessier, V. Betz, D. Neto, and T. Gopalsamy. Power-aware RAM mapping for FPGA embedded memory blocks. In ACM/SIGDA Int'l Symposium on Field Programmable Gate Arrays, pages 189--198, Monterey, CA, 2006.
28. K.O. Tinmaung, D. Howland, and R. Tessier. Power-aware FPGA logic synthesis using binary decision diagrams. In ACM/SIGDA Int'l Symposium on Field Programmable Gate Arrays, pages 148--155, Monterey, CA, 2007.
29. T. Tuan, S. Kao, A. Rahman, S. Das, and S. Trimberger. A 90nm low-power FPGA for battery-powered applications. IEEE Trans. On CAD of Integrated Circuits and Systems, 26(2):296--300, February 2007.
30. K. Vorwerk, M. Rahman, J. Dunoyer, Y.-C. Hsu, A. Kundu, and A. Kennings. A technique for minimizing power during FPGA placement. In IEEE International Conference on Field Programmable Logic and Applications, pages 233--238, Heidelberg, Germany, 2008.
31. Q. Wang and S. Roy. Power minimization by clock root gating. In IEEE/ACM Asia and South Pacific Design Automation Conference, pages 249--254, Kitakyushu, Japan, 2003.
32. Xilinx, Inc., San Jose, CA. Virtex-5 FPGA Data Sheet, 2007.

Index Terms

• Hardware

  • Electronic design automation

    • Physical design (EDA)