ABSTRACT
The analog placement algorithm Plantage, presented in this paper, generates placements for analog circuits with comprehensive placement constraints. Plantage is based on a hierarchically bounded enumeration of basic building blocks, using B*-trees. The practically relevant solution space is thereby enumerated quasi-complete. The sets of possible placements of the basic building blocks are represented and combined in a new efficient way, using enhanced shape functions. The result of Plantage is the Pareto front of placements with respect to different aspect ratios. The whole approach is deterministic, in contrast to existing analog placement algorithms.
- Rob A. Rutenbar, L. Richard Carley, John M. Cohn, and David J. Garrod. Analog Device-Level Layout Automation. Kluwer Academic Publishers, 1994.Google Scholar
- Alan Hastings. The Art of Analog Layout. Prentice-Hall, 2001.Google Scholar
- Enrico Malavasi and Alberto Sangiovanni-Vincentelli. Area routing for analog layout. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 12(8):1186--1197, August 1993.Google ScholarDigital Library
- D. W. Jepsen and C. D. Gellat Jr. Macro placement by monte carlo annealing. In IEEE International Conference on Computer Design (ICCD), pages 495--498, 1983.Google Scholar
- John M. Cohn, David J. Garrod, Rob A. Rutenbar, and L. Richard Carley. Koan/anagram ii: New tools for device-level analog placement and routing. IEEE Journal of Solid-State Circuits SC, 26(3):330--342, March 1991.Google ScholarCross Ref
- Koen Lampert, Georges Gielen, and Willy M. Sansen. A performancedriven placement tool for analog integrated circuits. IEEE Journal of Solid-State Circuits SC, 30(7):773--780, July 1995.Google ScholarCross Ref
- Enrico Malavasi, Edoardo Charbon, Eric Felt, and Alberto Sangiovanni-Vincentelli. Automation of ic layout with analog constraints. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 15(8):923--942, August 1996. Google ScholarDigital Library
- Pei-Ning Guo, Chung-Kuan Cheng, and Takeshi Yoshimura. An o-tree representation of non-slicing floorplan and its applications. In ACM/IEEE Design Automation Conference (DAC), volume 36, pages 268--273, June 1999. Google ScholarDigital Library
- H. Murata, K. Fujiyoshi, S. Nakatake, and Kajitani. VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 15(12):1518--1524, 1996. Google ScholarDigital Library
- S. Nakatake, K. Fujiyoshi, H. Murata, and Y. Kajitani. Module placement on BSG-structure and IC layout applications. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 484--493, 1996. Google ScholarDigital Library
- Yingxin Pang, Florin Balasa, Koen Lampaert, and Chung-Kuan Cheng. Block placement with symmetry constraints based on the o-tree non-slicing representation. In ACM/IEEE Design Automation Conference (DAC), pages 464--468, June 2000. Google ScholarDigital Library
- X. Hong., G. Huang, Y. Cai, J. Gu, S. Dong, C.-K. Cheng, and J. Gu. Corner block list: An effective and efficient topological representation of non-slicing floorplan. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2000. Google ScholarDigital Library
- Qiang Ma, Evangeline F. Y. Yong, and K. P. Pun. Analog placement with common centroid constraints. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2007. Google ScholarDigital Library
- Jai-Ming Lin and Yao-Wen Chang. Tcg-s: Orthogonal coupling of p-admissible representations for general floorplans. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 23(6):968--980, June 2004. Google ScholarDigital Library
- Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, and Shu-Wei Wu. B*-trees: A new representation for non-slicing floorplans. In ACM/IEEE Design Automation Conference (DAC), volume 37, pages 458--463, 2000. Google ScholarDigital Library
- Florin Balasa, Sarat C. Maruvada, and Karthik Krishnamoorthy. On the exploration of the solution space in analog placement with symmetry constraints. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 23(2):177--191, February 2004. Google ScholarDigital Library
- Ammar Nassaj, Jens Lienig, and Göran Jerke. A constraint-driven methodology for placement of analog and mixed-signal integrated circuits. In IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008.Google ScholarCross Ref
- Florian Balasa and Koen Lampaert. Symmetry within the sequencepair representation in the context of placement for analog design. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 19(7):721--731, July 2000. Google ScholarDigital Library
- Karthik Krishnamoorthy, Sarat C. Maruvada, and Florin Balasa. Fast evaluation of symmetric-feasible sequence-pairs for analog topological placement. In 5th IEEE Int. Conf. on ASIC (ASICON), pages 71--74, 2003.Google ScholarCross Ref
- Karthik Krishnamoorthy, Sarat C. Maruvada, and Florin Balasa. Topological placement with multiple symmetry groups of devices for analog layout design. In IEEE International Symposium on Circuits and Systems (ISCAS), pages 2032--2035, May 2007.Google ScholarCross Ref
- Lin Po-Hung and Lin Shyh-Chang. Analog placement based on novel symmetry-island formulation. In ACM/IEEE Design Automation Conference (DAC), pages 465--470, June 2007. Google ScholarDigital Library
- Yiu-Cheong Tam, Evangeline F. Y. Young, and Chris Chu. Analog placement with symmetry and other placement constraints. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2006. Google ScholarDigital Library
- David A. Johns and Ken Martin. Analog Integrated Circuit Design. John Wiley & Sons, 1997.Google Scholar
- H. Graeb, S. Zizala, J. Eckmueller, and K. Antreich. The sizing rules method for analog integrated circuit design. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 343--349, 2001. Google ScholarDigital Library
- Tobias Massier, Helmut Graeb, and Ulf Schlichtmann. Sizing rules for bipolar analog circuit design. In Design, Automation and Test in Europe (DATE), March 2008. Google ScholarDigital Library
- R. H. J. M. Otten. Efficient floorplan optimization. In IEEE International Conference on Computer Design (ICCD), pages 499--501, October 1983.Google Scholar
- Gerhard Zimmermann. A new area and shape function estimation technique for VLSI layouts. In ACM/IEEE Design Automation Conference (DAC), volume 25, pages 60--65, 1988. Google ScholarDigital Library
- J. Fisher and R. Koch. A highly linear CMOS buffer amplifier. IEEE Journal of Solid-State Circuits SC, 22:330--334, 1987.Google ScholarCross Ref
- Shinichi Kouda, Chikaaki Kodama, and Kunihiro Fujiyoshi. Improved method of cell placement with symmetry constraints for analog ic layout design. In ACM/SIGDA International Symposium on Physical Design (ISPD), April 2006. Google ScholarDigital Library
Recommendations
Routability-driven analytical placement for mixed-size circuit designs
ICCAD '11: Proceedings of the International Conference on Computer-Aided DesignDue to the significant mismatch between existing wirelength models and the congestion objective in placement, considering routability during placement is particularly significant for modern circuit designs. In this paper, a novel routability-driven ...
Routability-driven placement for hierarchical mixed-size circuit designs
DAC '13: Proceedings of the 50th Annual Design Automation ConferenceA wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements. Therefore, it is desirable to develop an effective routability-driven placer for modern mixed-size designs employing hierarchical ...
Comments