Synthesis of networks on chips for 3D systems on chips

ABSTRACT

Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (NoCs) are necessary to efficiently handle the 3D interconnect complexity. Designing power efficient NoCs for 3D SoCs that satisfy the application performance requirements, while satisfying the 3D technology constraints is a big challenge. In this work, we address this problem and present a synthesis approach for designing power-performance efficient 3D NoCs. We present methods to determine the best topology, compute paths and perform placement of the NoC components in each 3D layer. We perform experiments on varied, realistic SoC benchmarks to validate the methods and also perform a comparative study of the resulting 3D NoC designs with 3D optimized mesh topologies. The NoCs designed by our synthesis method results in large interconnect power reduction (average of 38%) and latency reduction (average of 25%) when compared to traditional NoC designs.

References

1. L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm", IEEE Computers, pp. 70--78, Jan. 2002.
2. P. Guerrier, A. Greiner,"A generic architecture for on-chip packet switched interconnections", Proc. DATE, pp. 250--256, March 2000.
3. G. De Micheli, L. Benini, "Networks on Chips: Technology and Tools", Morgan Kaufmann, First Edition, July, 2006.
4. K. Goossens et al., "A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification", DATE 2005.
5. S. Stergiou et al., "xpipesLite: a Synthesis Oriented Design Library for Networks on Chips", pp. 1188--1193, Proc. DATE 2005.
6. J. Hu, R. Marculescu, 'Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures', Proc. DATE, March 2003.
7. S. Murali, G. De Micheli, "SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs", Proc. DAC 2004.
8. S. Murali, G. De Micheli, "Bandwidth Constrained Mapping of Cores onto NoC Architectures", Proc. DATE 2004.
9. D. Bertozzi et al., "NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip", IEEE TPDS, Feb 2005.
10. A. Pinto et al., "Efficient Synthesis of Networks on Chip", ICCD 2003, pp. 146--150, Oct 2003.
11. W. H. Ho, T. M. Pinkston, "A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns", HPCA, 2003.
12. T. Ahonen et al. "Topology Optimization for Application Specific Networks on Chip", Proc. SLIP 04.
13. K. Srinivasan et al., "An Automated Technique for Topology and Route Generation of Application Specific On-Chip Interconnection Networks", Proc. ICCAD '05.
14. A. Hansson et al., "A Unified Approach to Constrained Mapping and Routing on Network-on-Chip Architectures", Proc. CODES-ISSS, 2005.
15. X. Zhu, S. Malik, "A Hierarchical Modeling Framework for On-Chip Communication Architectures", ICCD 2002, pp. 663--671, Nov 2002.
16. J. Xu et al., "A design methodology for application-specific networks-on-chip", ACM TECS, May 2006.
17. S. Murali et al., "Designing Application-Specific Networks on Chips with Floorplan Information", pp. 355--362, ICCAD 2006.
18. W. J. Dally, "Performance Analysis of k-ary n-cube Interconnection Networks", IEEE Transactions on Computers, Vol. 39, No. 6, pp. 775--785, 1990.
19. K. Banerjee et al., "3-D ICs: ANovel Chip Design for Deep-Submicrometer Interconnect Performance & SoC Integration", Proc. of IEEE, 2001.
20. B. Goplen and S. Sapatnekar, "Thermal Via Placement in 3D ICs", Proc. Intl. Symposium on Physical Design, pp. 167, 2005.
21. J. Cong et al., "A thermal-driven floorplanning algorithm for 3D ICs", ICCAD 2004.
22. W.-L. Hung et al., "Interconnect and thermal-aware floorplanning for 3D microprocessors", Proc. ISQED, March 2006.
23. S. K. Lim, "Physical Design for 3D System on Package", IEEE Design & Test of Computers, vol. 22(6), pp. 532539, 2005.
24. P. Zhou et al., "3D-STAF: Scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits", ICCAD 2007.
25. N. Miyakawa et al., "New Multi-Layer Stacking Technology and Trial Manufacture", 3-D Architectures for Semiconductor Integration and Packaging, Oct 2007.
26. R. Weerasekara et al., "Extending Systems-on-Chip to the Third Dimension: Performance, Cost and Technological Tradeoffs", Proc. ICCAD, 2007.
27. V. F. Pavlidis and E. G. Friedman, "Topologies for networks-onchip", Proc. SOCC, 2006.
28. B. Feero and P. P. Pande, "Performance evaluation for three-dimensional networks-on-chip", Proc. ISVLSI, 2007.
29. C. Addo-Quaye, "Thermal-Aware Mapping and Placement for 3-D NoC Designs", Proc. SOCC, 2005.
30. J. Kim et al., "A novel dimensionally-decomposed router for on-chip communication in 3d architectures", ISCA, 2007.
31. F. Li et al., "Design and Management of 3D Chip Multiprocessors Using Network-in-Memory", ISCA, pp. 130--141, 2006.
32. D. Park et al., "MIRA: A Multi-Layered On-Chip Interconnect Router Architecture", Proc. ISCA, 2008.
33. I. Loi, F. Angiolini, L. Benini, Supporting vertical links for 3D networks on chip: toward an automated design and analysis flow, Proc. Nano-Nets, 2007.
34. S. Boyd and L. Vandenberghe, "Convex Optimization", Cambridge University Press, 2004.
35. Package available at: http://sourceforge.net/projects/lpsolve
36. S. N. Adya, I. L. Markov, "Fixed-outline Floorplanning: Enabling Hierarchical Design", IEEE TVLSI, Dec 2003.