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- Yella ASechen C(2017) Improved lagrangian relaxation-based gate size and V T assignment for very large circuits 2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)10.1109/PRIME-LA.2017.7899169(1-4)Online publication date: Feb-2017
- Reimann TSze CReis R(2015)Gate sizing and threshold voltage assignment for high performance microprocessor designsThe 20th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2015.7059007(214-219)Online publication date: Jan-2015
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