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A new algorithm for simultaneous gate sizing and threshold voltage assignment

Published: 29 March 2009 Publication History

Abstract

Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven heuristics or based on rounding continuous optimization solutions. Sensitivity-drive heuristics are easily trapped in local optimum and the rounding is subject to remarkable errors. In this paper, we propose a systematic combinatorial approach for simultaneous gate sizing and Vt assignment. The core ideas of this approach include consistency relaxation and coupled bi-directional search. Our algorithm is compared with a state-of-the-art previous work on benchmark circuits. The results from our algorithm can lead to about 24% less power dissipation subject to the same timing constraints.

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Cited By

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  • (2024)Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height DesignsProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3656243(1-6)Online publication date: 23-Jun-2024
  • (2017) Improved lagrangian relaxation-based gate size and V T assignment for very large circuits 2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)10.1109/PRIME-LA.2017.7899169(1-4)Online publication date: Feb-2017
  • (2015)Gate sizing and threshold voltage assignment for high performance microprocessor designsThe 20th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2015.7059007(214-219)Online publication date: Jan-2015
  • Show More Cited By

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    cover image ACM Conferences
    ISPD '09: Proceedings of the 2009 international symposium on Physical design
    March 2009
    208 pages
    ISBN:9781605584492
    DOI:10.1145/1514932
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    Published: 29 March 2009

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    Author Tags

    1. gate sizing
    2. threshold voltage assignment

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    March 29 - April 1, 2009
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    Cited By

    View all
    • (2024)Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height DesignsProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3656243(1-6)Online publication date: 23-Jun-2024
    • (2017) Improved lagrangian relaxation-based gate size and V T assignment for very large circuits 2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)10.1109/PRIME-LA.2017.7899169(1-4)Online publication date: Feb-2017
    • (2015)Gate sizing and threshold voltage assignment for high performance microprocessor designsThe 20th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2015.7059007(214-219)Online publication date: Jan-2015
    • (2014)Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian RelaxationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.230584733:4(546-557)Online publication date: 1-Apr-2014
    • (2013)Discrete sizing for leakage power optimization in physical designACM Transactions on Design Automation of Electronic Systems10.1145/2390191.239020618:1(1-11)Online publication date: 16-Jan-2013
    • (2013)Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2013.6654627(84-89)Online publication date: Aug-2013
    • (2013)Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)10.1109/ISCAS.2013.6572398(2549-2552)Online publication date: May-2013
    • (2012)An efficient algorithm for library-based cell-type selection in high-performance low-power designsProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429427(226-232)Online publication date: 5-Nov-2012
    • (2012)Algorithms for Gate Sizing and Device Parameter Selection for High-Performance DesignsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.219627931:10(1558-1571)Online publication date: 1-Oct-2012
    • (2012)Modeling Energy-Time Trade-Offs in VLSI ComputationIEEE Transactions on Computers10.1109/TC.2011.4061:4(530-547)Online publication date: 1-Apr-2012
    • Show More Cited By

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