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An area reduction method for digital filter using redundancy of SD number system

Published: 15 February 2009 Publication History

Abstract

In this paper, an area efficient digital filter design method is proposed. The conventional area efficient filter design methods have the problems of long critical path delay since they make deep logic depth due to adder sharing. In this paper, we propose a method which can reduce filter size using the redundancy of the signed digit (SD) number system based on the flattened-coefficient method which can share adders while maintain the critical path delay. Simulation results show that the proposed structure can save the number of adders and registers 22% and 26%, respectively, than the conventional methods can do.

References

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A. Dempster and M. D. Macleod, "Use of minimum-adder multiplier blocks in FIR digital filters," IEEE Trans. Circuits Syst. II, vol.42, no. 9, pp. 569--577, Sep. 1995.
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D. R. Bull and D. H. Horrocks, "Primitive operator digital filter," Proc. Inst. Ele. Eng. Circuits, Devices and Systems, vol. 138, no. 3, pp.401--412, Jun. 1991.
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R. Hartley, "Subexpression sharing in filters using canonical signed digit multipliers," IEEE Trans. Circuits Syst. II, vol.43, no. 10, pp. 677--688, Oct. 1996.
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M. Martinez-Peiro, E. I. Boemo, and L. Wanhammar, "Design of High-Speed Multiplierless Filters Using a Nonrecursive Signed Common Subexpression Algorithm," IEEE Trans. Circuits Syst. II, vol. 49, no.3, pp.196--203, Mar. 2002.
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S. H. Yoon, J. W. Chong, "FIR Digital Filter Implementation using flattened coefficient," in Proc. IEEE Int. Symp. Circuits and Systems, Geneva, vol. 3, pp.363--366, May 2000.
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S. H. Yoon, J. W. Chong, C. H. Lin, "An Area Optimization Method for Digital Filter Design," ETRI J., vol. 26, no.4, pp.545--553, Dec. 2004.
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  1. An area reduction method for digital filter using redundancy of SD number system

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    cover image ACM Conferences
    ICUIMC '09: Proceedings of the 3rd International Conference on Ubiquitous Information Management and Communication
    February 2009
    704 pages
    ISBN:9781605584058
    DOI:10.1145/1516241
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 15 February 2009

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    Author Tags

    1. adder sharing
    2. architecture
    3. digital filter
    4. flattened coefficient

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