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Energy efficient architecture of sensor network node based on compression accelerator

Published: 10 May 2009 Publication History

Abstract

In this paper, we propose an energy efficient architecture of wireless sensor network node. It consists of a general-purpose processor and several compression accelerators. To verify the low energy consumption of this architecture, we implement a baseband chip of sensor node by 1-poly 6-metal 0.18um CMOS technology, in which a hardware accelerator is realized based on a distributed wavelet compression algorithm. Our measurements show that the compression accelerator based architecture reduces over 98% energy consumption compared with the traditional solution.

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Cited By

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  • (2017)Dynamic Voltage-Frequency and Workload Joint Scaling Power Management for Energy Harvesting Multi-Core WSN Node SoCSensors10.3390/s1702031017:2(310)Online publication date: 8-Feb-2017
  • (2013)PKF: A communication cost reduction schema based on Kalman filter and data prediction for Wireless Sensor Networks2013 IEEE International SOC Conference10.1109/SOCC.2013.6749663(73-78)Online publication date: Sep-2013
  • (2011)An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive CompressionIEICE Transactions on Electronics10.1587/transele.E94.C.1220E94-C:7(1220-1228)Online publication date: 2011
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      cover image ACM Conferences
      GLSVLSI '09: Proceedings of the 19th ACM Great Lakes symposium on VLSI
      May 2009
      558 pages
      ISBN:9781605585222
      DOI:10.1145/1531542
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 10 May 2009

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      Author Tags

      1. chip design
      2. compression accelerator
      3. energy efficient
      4. wireless sensor network

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      GLSVLSI '09: Great Lakes Symposium on VLSI 2009
      May 10 - 12, 2009
      MA, Boston Area, USA

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      Overall Acceptance Rate 312 of 1,156 submissions, 27%

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      Cited By

      View all
      • (2017)Dynamic Voltage-Frequency and Workload Joint Scaling Power Management for Energy Harvesting Multi-Core WSN Node SoCSensors10.3390/s1702031017:2(310)Online publication date: 8-Feb-2017
      • (2013)PKF: A communication cost reduction schema based on Kalman filter and data prediction for Wireless Sensor Networks2013 IEEE International SOC Conference10.1109/SOCC.2013.6749663(73-78)Online publication date: Sep-2013
      • (2011)An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive CompressionIEICE Transactions on Electronics10.1587/transele.E94.C.1220E94-C:7(1220-1228)Online publication date: 2011
      • (2010)A compare-and-write ferroelectric nonvolatile flip-flop for energy-harvesting applicationsThe 2010 International Conference on Green Circuits and Systems10.1109/ICGCS.2010.5542984(646-650)Online publication date: Jun-2010

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