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Low power and high performance sram design using bank-based selective forward body bias

Published: 10 May 2009 Publication History

Abstract

Leakage power consumption is a large fraction of the total power consumption in contemporary VLSI designs. Since memories occupy a large portion of the total area of many high-performance ICs, it is crucial to reduce the leakage energy of memories. This problem is particularly aggravated for memories implemented in the 45nm technology node, since these processes exhibit significantly higher leakage power. For these memories, leakage is a significant problem not only from a power point of view, but also from a performance degradation standpoint. In this paper, we quantify this problem and provide a solution, using a 512KByte SRAM implemented in a 45nm bulk process as a design example. We show that implementing the SRAM as a monolithic memory results in increased delay as well as power. We illustrate a methodology to optimally reduce leakage power and improve performance in memories by splitting the memory array into word line groups (WLGs) which are selectively forward body biased when accessed. We present a derivation of optimal number of WLGs and the forward body bias voltage value, and show that our approach results in a 9:2% access time reduction, and a 53:4% reduction in power during a read operation. Our approach also achieves an 18% reduction in power during a write operation and a 69% leakage power improvement. The area overhead of our scheme is 7:2% compared to a monolithic memory.

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Cited By

View all
  • (2012)Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAMIntegration, the VLSI Journal10.1016/j.vlsi.2011.07.00145:1(33-45)Online publication date: 1-Jan-2012
  • (2011)PVT-tolerant 7-Transistor SRAM Optimization via Polynomial RegressionProceedings of the 2011 International Symposium on Electronic System Design10.1109/ISED.2011.11(39-44)Online publication date: 19-Dec-2011
  • (2010)P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP2010 11th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2010.5450470(176-183)Online publication date: Mar-2010

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    cover image ACM Conferences
    GLSVLSI '09: Proceedings of the 19th ACM Great Lakes symposium on VLSI
    May 2009
    558 pages
    ISBN:9781605585222
    DOI:10.1145/1531542
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 10 May 2009

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    Author Tags

    1. body bias
    2. high performance
    3. low power

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    May 10 - 12, 2009
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    View all
    • (2012)Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAMIntegration, the VLSI Journal10.1016/j.vlsi.2011.07.00145:1(33-45)Online publication date: 1-Jan-2012
    • (2011)PVT-tolerant 7-Transistor SRAM Optimization via Polynomial RegressionProceedings of the 2011 International Symposium on Electronic System Design10.1109/ISED.2011.11(39-44)Online publication date: 19-Dec-2011
    • (2010)P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP2010 11th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2010.5450470(176-183)Online publication date: Mar-2010

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