Hirendu Vaishnav
Massoud Pedram
- 1.C. L. Berman and J. L. Carter. The fanout problem: From theory to practice. In C. L. Seitz, editor, Advanced Research in VLSI: Proceeding8 of the 1989 Decennial Caltech Conference, pages 69-99. MIT Press, May 1989. Google Scholar
Digital Library
- 2.D. Coppersmith, M. M. Klawe, and N. J. Pippenger. Alphabetic minimax trees of degree at most t. SIAM Jo~rnal of Computing, 15:189-192, 1986. Google ScholarDigital Library
- 3.Shimon Even. Graph Algorithms. Computer Science press, Rockville, Maryland, first edition, 1979. Google ScholarDigital Library
- 4.M.C. Golumbic. Combinatorial merging. IEEE Transactions on Computers, 25(11):514-526, 1976.Google Scholar
- 5.R. L. Graham, D. E. Knuth, and O. Pataslmik. Concrete Mathematics: A Foundation for Computer Science. Addison- Wesley Publishing Company, Reading, Massachusetts, first edition, 1988. Google ScholarDigital Library
- 6.H. J. Hoover, M. M. Klawe, and N. J. Pippenger. Bounding fanout in logical networks. Journal of the Association for Computing Machinery, 31(1):13-18, January 1984. Google ScholarDigital Library
- 7.T. C. Hu, D. J. Kleitman, and J. K. Tamaki. Binary trees optimum under various criteria. SIAM Journal of Applied Mathematics, 37(2):246-256, October 1979.Google ScholarDigital Library
- 8.T. C. Hu and A. C. Tucker. Optimal computer search trees and varaible-length alphabetical codes. SIAM Journal of Applied Mathematics, 21(4):514-532, December 1971.Google ScholarDigital Library
- 9.International Workshop on Logic Synthesis, MCNC, North Carolina. Logic synthesis benchmarks. May 1991.Google Scholar
- 10.D. G. Kirkpatrick and M. M. Klawe. Alphabetic minimax trees. SIAM Journal of Computing, 14(3):514-526, 1985.Google ScholarDigital Library
- 11.J.M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich. GORDIAN: VLSI placement by quadratic programming and slicing optimization. IEEE Transactions on Computer-Aided Design, CAD-10:350--365, March 1991.Google Scholar
- 12.D. Knuth. The Art of Computer Programming. Addison- Wesley, 1973. Google ScholarDigital Library
- 13.M. Pedram and N. Bhat. Layout driven technology mapping. In Proceedings of the ~8th Design Automation Conference, pages 99-105, June 1991. Google ScholarDigital Library
- 14.J. Reed, A. Sangiovanni-Vincentelli, and M. Santamauro. A new symbolic channel router: YACR2. In IEEE Transactions on Computer-Aided Design of integrated Circuits and Systems, pages 208-219, July 1985.Google Scholar
- 15.K. J. Singh and A. Sangiovanni-Vincentelli. A heuristic algorithm for the fanout problem. In Proceedings of the ~7th Design Automation Conference, pages 357-360, June 1990. Google ScholarDigital Library
- 16.H. J. Touati, C. W. Moon, R. K. Brayton, and A. Wang. Performance-oriented technology mapping. In Proceedings of the Sixth M.L T. Conference on Advanced Research in VLSI, pages 79-97, April 1990. Google ScholarDigital Library
- 17.Herve Touati. Performance Oriented Technology Mapping. PhD thesis, University of California, Berkeley, 1990. Google ScholarDigital Library
- 18.H. Vaishnav and M. Pedram. Alphabetic fanout optimiza~ tion. Technical Report CEng 92-15, University of Southern California, 1992.Google Scholar
Index Terms
- Routability-driven fanout optimization
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