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Untwist your brain: efficient debugging and diagnosis of complex assertions

Published: 26 July 2009 Publication History

Abstract

Assertions are recognized in the industry to be a major improvement in functional RTL verification flows. Today's standard assertion languages, such as SVA [1] and PSL [2], are very expressive, capable of describing sophisticated temporal design behavior at different abstraction levels. Nevertheless, most assertion users stick to writing simple assertions because of the intricacy and effort required to debug complex assertions -- one of the major bottlenecks in assertion based verification.
We present debugging and diagnosis techniques that automatically identify those parts of an assertion that cause the assertion to fail for a given design and that provide additional automation to efficiently identify the root cause of the failure. These techniques enable major effort savings when working with complex assertions, allowing engineers to use the full capabilities of assertion languages. This enables further productivity and quality improvements in functional verification by lifting mainstream assertion usage to higher abstraction levels such as efficient capture and verification of high-level design features, operations, and transactions. Advanced debugging automation is key for this progress - solving a problem that many designers and verification engineers face in their daily work.

References

[1]
IEEE Standard 1800--2005 SystemVerilog: Unified Hardware Design, Specification and Verification Language, USA, 2005.
[2]
IEEE Standard 1850--2005 Property Specification Language (PSL), IEEE, Inc., New York, NY, USA, 2005.
[3]
http://www.onespin-solutions.com/360mv.php
[4]
R. Wille, G. Fey, M. Messing, R. Drechsler et. al.; Identifying a subset of SystemVerilog Assertions for Efficient Bounded Model Checking, Conf. on Digital System Design (DSD), 2008.
[5]
G. Fey, S. Staber, R. Bloem, R. Drechsler. Automatic fault localization for property checking. IEEE Trans. on CAD of Integrated Circuits and Systems, 27:1138--1149, 2008.
[6]
D. Bustan and J. Havlicek. Some complexity results for SystemVerilog Assertions. CAV 2006, volume 4144 of LNCS.
[7]
J. Bormann, S. Beyer, T. Blackmore, et al. Complete Formal Verification of TriCore2 and Other Processors, DVCon 2007

Cited By

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  • (2023)Formal Property Verification for Early Discovery of Functional Flaws in Digital Designs: A Designer's Guide2023 26th Euromicro Conference on Digital System Design (DSD)10.1109/DSD60849.2023.00105(734-741)Online publication date: 6-Sep-2023
  • (2015)SystemVerilog assertion debugging: A visualization and pattern matching model2015 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)10.1109/PACRIM.2015.7334867(385-390)Online publication date: Aug-2015
  • (2014)System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation2014 15th International Microprocessor Test and Verification Workshop10.1109/MTV.2014.23(55-60)Online publication date: Dec-2014
  • Show More Cited By

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  1. Untwist your brain: efficient debugging and diagnosis of complex assertions

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    cover image ACM Conferences
    DAC '09: Proceedings of the 46th Annual Design Automation Conference
    July 2009
    994 pages
    ISBN:9781605584973
    DOI:10.1145/1629911
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 26 July 2009

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    Author Tags

    1. SystemVerilog assertions
    2. assertions
    3. debugging
    4. fault localization
    5. functional verification
    6. root cause analysis

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    DAC '09: The 46th Annual Design Automation Conference 2009
    July 26 - 31, 2009
    California, San Francisco

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    View all
    • (2023)Formal Property Verification for Early Discovery of Functional Flaws in Digital Designs: A Designer's Guide2023 26th Euromicro Conference on Digital System Design (DSD)10.1109/DSD60849.2023.00105(734-741)Online publication date: 6-Sep-2023
    • (2015)SystemVerilog assertion debugging: A visualization and pattern matching model2015 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)10.1109/PACRIM.2015.7334867(385-390)Online publication date: Aug-2015
    • (2014)System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation2014 15th International Microprocessor Test and Verification Workshop10.1109/MTV.2014.23(55-60)Online publication date: Dec-2014
    • (2012)SystemVerilog AssertionsIEEE Design & Test10.1109/MDT.2012.218333629:2(23-31)Online publication date: 1-Apr-2012
    • (2011)Generating compact assertions for control-based logic signals2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2011.6026268(1-4)Online publication date: Aug-2011

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