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GPU-based parallelization for fast circuit optimization

Published: 26 July 2009 Publication History

Abstract

The progress of GPU (Graphics Processing Unit) technology opens a new avenue for boosting computing power. This work is an attempt to exploit GPU for accelerating VLSI circuit optimization. We propose GPU-based parallel computing techniques and apply them on simultaneous gate sizing and threshold voltage assignment, which is often employed in practice for performance and power optimization. These techniques are aimed to fully utilize the benefits of GPU through efficient task scheduling and memory organization. Compared to conventional sequential computation, our techniques can provide up to 56x speedup without any sacrifice on solution quality.

References

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K. Gulati and S. Khatri. Towards Acceleration of Fault Simulation using Graphics Processing Units. In Proceedings of the ACM/IEEE DAC, 2008.
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Z. Feng and P. Li. Multigrid on GPU: Tackling Power Grid Analysis on Parallel SIMT Platforms. In Proceedings of the ACM/IEEE ICCAD, 2008.
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O. Coudert. Gate sizing for constrained delay/power/area optimization. In IEEE Trans. VLSI, 1997.
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L. Wei, Z. Chen, K. Roy and V. De. Design and Optimization of Dual Threshold Circuits for Low Voltage Low Power Application. In IEEE Trans. VLSI, 1999.
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S. Sirichotiyakul, T. Edwards, C. Oh, J. Zuo, A. Dharchoudhury, R. Panda and D. Blaauw. Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing. In Proceedings of the ACM/IEEE DAC, 1999.
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T. Wu and A. Davoodi. PaRS: Fast and Near-Optimal Grid-Based Cell Sizing for Library-Based Design. In Proceedings of the ACM/IEEE ICCAD, 2008.
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Y. Liu and J. Hu. A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment. In Proceedings of the ACM ISPD, 2009.
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L. P. P. P. van Ginneken. Buffer Placement in Distributed RC-Tree Networks for minimal Elmore Delay. In IEEE ISCS, 1990.
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D. Nguyen, A. Davare, M. Orshansky, D. Chinnery, B. Thompson and K. Keutzer. Minimizion of Dynamic and Static Power Through Joint Assignement of Threshold Voltages and Sizing Optimization. In ISLPED, 2003.
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Cited By

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  • (2015)GPU acceleration for PCA-based statistical static timing analysisProceedings of the 2015 33rd IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2015.7357180(674-679)Online publication date: 18-Oct-2015
  • (2012)Accelerating thermal simulations of 3D ICs with liquid cooling using neural networksProceedings of the great lakes symposium on VLSI10.1145/2206781.2206787(15-20)Online publication date: 3-May-2012
  • (2012)Neural Network-Based Thermal Simulation of Integrated Circuits on GPUsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.217423631:1(23-36)Online publication date: 1-Jan-2012
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    cover image ACM Conferences
    DAC '09: Proceedings of the 46th Annual Design Automation Conference
    July 2009
    994 pages
    ISBN:9781605584973
    DOI:10.1145/1629911
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 26 July 2009

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    Author Tags

    1. GPU
    2. VLSI circuit optimization
    3. parallel computing

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    DAC '09: The 46th Annual Design Automation Conference 2009
    July 26 - 31, 2009
    California, San Francisco

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    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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    Cited By

    View all
    • (2015)GPU acceleration for PCA-based statistical static timing analysisProceedings of the 2015 33rd IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2015.7357180(674-679)Online publication date: 18-Oct-2015
    • (2012)Accelerating thermal simulations of 3D ICs with liquid cooling using neural networksProceedings of the great lakes symposium on VLSI10.1145/2206781.2206787(15-20)Online publication date: 3-May-2012
    • (2012)Neural Network-Based Thermal Simulation of Integrated Circuits on GPUsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.217423631:1(23-36)Online publication date: 1-Jan-2012
    • (2012)Accelerating Gate Sizing Using Graphics Processing UnitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.216453931:1(160-164)Online publication date: 1-Jan-2012
    • (2012)An effective method to use GPU for rectangle packing10th IEEE International NEWCAS Conference10.1109/NEWCAS.2012.6328973(129-132)Online publication date: Jun-2012
    • (2012)Optimisation and Parallelism in Synchronous Digital Circuit SimulatorsProceedings of the 2012 IEEE 15th International Conference on Computational Science and Engineering10.1109/ICCSE.2012.23(94-101)Online publication date: 5-Dec-2012
    • (2012)Scan Test Power Simulation on GPGPUsProceedings of the 2012 IEEE 21st Asian Test Symposium10.1109/ATS.2012.23(155-160)Online publication date: 19-Nov-2012
    • (2012)Thread affinity mapping for irregular data access on shared Cache GPGPU17th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2012.6165038(659-664)Online publication date: Jan-2012
    • (2011)Gate-Level Simulation with GPU ComputingACM Transactions on Design Automation of Electronic Systems10.1145/1970353.197036316:3(1-26)Online publication date: 1-Jun-2011
    • (2011)Design and Implementation of a Throughput-Optimized GPU Floorplanning AlgorithmACM Transactions on Design Automation of Electronic Systems10.1145/1970353.197035616:3(1-21)Online publication date: 1-Jun-2011
    • Show More Cited By

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