Bo Yao
ABSTRACT
A deterministic broadside test generation procedure is proposed for transition path delay faults. Under this fault model, a path delay fault is detected if and only if all the individual transition faults along the path are detected by the same test. This is important for detecting both small and large delay defects. To handle the complexity of test generation, the procedure consists of five sub-procedures: a test generation procedure for transition faults, a preprocessing procedure that identifies undetectable transition path delay faults without performing test generation, a fault simulation procedure that identifies transition path delay faults that are detected by the tests for transition faults, a heuristic procedure similar to dynamic test compaction for transition faults that generates tests without backtracking on decisions made for previously detected faults, and a complete branch-and-bound procedure. Experimental results show that for most of the transition path delay faults in benchmark circuits either a test is found or the fault is identified as undetectable.
- Z. Barzilai and B. Rosen, "Comparison of AC self-testing procedures," in Proc. Int. Test Conf., 1983, pp. 89--94.Google Scholar
- J. L. Carter, V. S. Iyengar, and B. K. Rosen, "Efficient test coverage determination for delay faults," in Proc. Int. Test Conf., 1987, pp. 418--427.Google Scholar
- G. L. Smith, "Model for delay faults based upon paths," in Proc. Int. Test Conf., 1985, pp. 342--349.Google Scholar
- I. Pomeranz, S. M. Reddy, and J. H. Patel, "On double transition faults as a delay fault model," in Proc. Great Lakes Symp. VLSI, 1996, pp. 282--287. Google ScholarDigital Library
- K. Heragu, J. H. Patel, and V. D. Agrawal, "Segment delay faults: A new fault model," in Proc. 14th VLSI Test Symp., 1996, pp. 32--39. Google ScholarDigital Library
- M. Sharma and J. H. Patel, "Testing of critical paths for delay faults," in Proc. Int. Test Conf., 2001, pp. 634--641. Google ScholarDigital Library
- Y. Shao, I. Pomeranz, and S. M. Reddy, "On generating high quality tests for transition faults," in Proc. Asian Test Symp., 2002, pp. 1--8. Google ScholarDigital Library
- I. Pomeranz and S. M. Reddy, "Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects," IEEE Trans. VLSI Syst., Vol. 16, No. 1, January 2008, pp.98--107. Google ScholarDigital Library
- P. Goel and B. C. Rosales, "Test Generation and Dynamic Compaction of Tests," Digest of Papers 1979 Test Conf., pp. 189--192, October 1979.Google Scholar
- M. Abramovici, J. J. Kulikowski, P. R. Menon, and D. T. Miller, "SMART and FAST: Test Generation for VLSI Scan-Design Circuits," IEEE Design & Test of Computers, Vol. 3, No. 4, pp.43--54, August, 1986. Google ScholarDigital Library
- I. Pomeranz, L. N. Reddy, and S. M. Reddy, "COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits," in Proc. Int. Test Conf., 1991, pp194--203. Google ScholarDigital Library
- J. Rajski and H. Cox, "A method to calculate necessary assignments in algorithmic test pattern generation," in Proc. Int. Test Conf., 1990, pp. 25--34.Google Scholar
Index Terms
- Deterministic broadside test generation for transition path delay faults
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