Anuj Pushkarna
ABSTRACT
Transistor aging effects (NBTI and PBTI) impact the reliability of SRAM in nano-scale CMOS technologies. In this research, the combined effect of NBTI and PBTI on power gated SRAM is analyzed. Optimal source biasing in the standby mode is presented as an effective method for guard-banding against the aging effects. The simulations results in a predictive 32nm technology shows maximum of 1.6% reduction in standby SNM over 5 year lifetime. For optimum operation, by decreasing the standby source bias voltage by only 0.012 volts, the SNM is safely margined for 5 year life time. This guard-banding comes at an insignificant power overhead of 0.6% for applied worse case scenarios. Given the insignificant power overhead with such guard-banding, it is concluded that adaptive tuning of the source biasing voltage is not required, given the not so negligible complexity and overhead associated with adaptive techniques.
- Zhang, Bhattacharya, Chen; "SRAM Design on 65nm CMOS with Dynamic Sleep Transistor for Leakage Reduction", Solid-State Circuits, IEEE Journal of Publication, Date: April 2005 Volume: 40,Issue: 4 pp: 895--901Google Scholar
- K. Kang, et. al., "Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis," IEEE Transactions on Computer Aided Design of Integrated Circuits and System, vol. 26, no. 10, pp. 1770--1781, Oct. 2007 Google ScholarDigital Library
- Predictive Technology Models (PTM): http://www.eas.asu.edu/~ptm/Google Scholar
- PTM Reliability models (NBTI) http://www.eas.asu.edu/~ptm/Google Scholar
- S. Mukhopadhyay, et. al.; "Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nanoscaled CMOS", IEEE Vol. 24, No. 12, December 2005.Google Scholar
- R. Vattikonda, W. Wang, Y. Cao, "Modeling and minimization of PMOS NBTI effect for robust nanometer design," DAC, pp. 1047--1052, 2006. Google ScholarDigital Library
- Zhang, Guo; "Active Leakage Control with Sleep Transistors and Body Bias". Symposium on Low Power Electronics and Design, 2005.Google Scholar
Index Terms
- Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS
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