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Transistor sizing of custom high-performance digital circuits with parametric yield considerations

Published: 13 June 2010 Publication History

Abstract

Transistor sizing is a classic Computer-Aided Design problem that has received much attention in the literature. Due to the increasing importance of process variations in deep sub-micron circuits, nominal circuit tuning is not sufficient, and the sizing problem warrants revisiting. This paper addresses the sizing problem statistically in which transistor sizes are automatically adjusted to maximize parametric yield at a given timing performance, or maximize performance at a required parametric yield. Specifically, we describe an implementation of a statistical tuner using interior point nonlinear optimization with an objective function that is directly dependent on statistical process variation. Our results show that for process variation sensitive circuits, consisting of thousands of independently tunable devices, a statistically aware tuner can give more robust, higher yield solutions when compared to deterministic circuit tuning and is thus an attractive alternative to the Monte Carlo methods that are typically used to size devices in such circuits. To the best of our knowledge, this is the first publication of a working system to optimize device sizes in custom circuits using a process variation aware tuner.

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  • (2019)Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuitsIET Circuits, Devices & Systems10.1049/iet-cds.2018.561613:7(979-987)Online publication date: 22-Oct-2019
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      cover image ACM Conferences
      DAC '10: Proceedings of the 47th Design Automation Conference
      June 2010
      1036 pages
      ISBN:9781450300025
      DOI:10.1145/1837274
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      Published: 13 June 2010

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      1. custom circuits
      2. optimization

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      View all
      • (2019)Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuitsIET Circuits, Devices & Systems10.1049/iet-cds.2018.561613:7(979-987)Online publication date: 22-Oct-2019
      • (2016)Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield GradientACM Transactions on Design Automation of Electronic Systems10.1145/289681921:4(1-27)Online publication date: 18-May-2016
      • (2016)Emulation-Based Analysis of System-on-Chip Performance Under VariationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.255124324:12(3401-3414)Online publication date: 1-Dec-2016
      • (2015)An efficient algorithm for statistical timing yield optimizationProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744796(1-6)Online publication date: 7-Jun-2015
      • (2015)Variation-aware approaches with power improvement in digital circuitsIntegration, the VLSI Journal10.1016/j.vlsi.2014.07.00148:C(83-100)Online publication date: 1-Jan-2015
      • (2012)Reversible statistical max/min operationProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228554(1067-1073)Online publication date: 3-Jun-2012
      • (2011)An Architecture for Fault-Tolerant Computation with Stochastic LogicIEEE Transactions on Computers10.1109/TC.2010.20260:1(93-105)Online publication date: 1-Jan-2011
      • (2010)Timing yield optimization via discrete gate sizing using globally-informed delay PDFsProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133549(570-577)Online publication date: 7-Nov-2010
      • (2010)Active learning framework for post-silicon variation extraction and test cost reductionProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133538(508-515)Online publication date: 7-Nov-2010
      • (2010)Timing yield optimization via discrete gate sizing using globally-informed delay PDFs2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2010.5654205(570-577)Online publication date: Nov-2010
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