Dimin Niu
Yuan Xie
ABSTRACT
The memristor, known as the fourth basic two-terminal circuit element, has attracted many research interests since the first real device was developed by HP labs in 2008. The nano-scale memristive device has the potential to construct some novel computing systems because of its distinctive characters, such as non-volatility, non-linearity, low-power, and good scalability. These electrical characteristics of memristors are mainly determined by the material characteristic and the fabrication process. For example, process variations may cause the deviation of the actual electrical behavior of memristors from the original design and result in the malfunction of the device. Therefore, it is very important to understand and characterize the impact of process variations on the electrical behaviors of the memristor and its implication to the circuit design. In this paper, we analyze the impact of the geometry variations on the electrical characteristics of the memristor. Two parameters - NARD (Normalized Accumulative Resistance Deviation) and NAARD (Normalized Accumulative Absolute Resistance Deviation), are introduced to measure the fluctuation of the overall internal state (or the resistance) of a memristor under the impact of process variations. Based on our analysis, Monte-Carlo simulations are conducted to evaluate the device mismatch effects in the memristor-based memory.
- L. Chua. Memristor-the missing circuit element. IEEE Transactions on Circuit Theory, 18(5):507--519, Sep 1971.Google Scholar
Cross Ref
- D. B. Strukov et al. The missing memristor found. In Nature, volume 453, pages 80--83, 2008.Google Scholar
- Y. Ho, G. M. Huang, and P. Li. Nonvolatile memristor memory: device characteristics and design implications. In ICCAD 2009., Nov. 2009. Google ScholarDigital Library
- Y. V. Pershin and M. D. Ventra. Experimental demonstration of associative memory with memristive neural networks. In Nature Precedings, 2009.Google ScholarCross Ref
- H. Choi et al. An electrically modifiable synapse array of resistive switching memory. Nanotechnology, 2009.Google Scholar
- Y. V. Pershin and M. D. Ventra. Practical approach to programmable analog circuits with memristors. ArXiv e-prints, August 2009.Google Scholar
- A. Asenov, S. Kaya, and A. R. Brown. Intrinsic parameter fluctuations in decananometer mosfets introduced by gate line edge roughness. IEEE Transactions on Electron Devices, 50(5):1254--1260, May 2003.Google ScholarCross Ref
- P. Oldiges et al. Modeling line edge roughness effects in sub 100 nanometer gate length devices. In SISPAD., pages 131--134, 2000.Google ScholarCross Ref
- G. Roy et al. Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-mosfets. IEEE Transactions on Electron Devices, 53(12):3063--3070, Dec. 2006.Google ScholarCross Ref
- S. H. Jo, K. Kim, and W. Lu. High-density crossbar arrays based on a si memristive system. In Nano Lett., volume 9, pages 870--874, 2009.Google ScholarCross Ref
- X. Wang et al. Spintronic memristor through spin-torque-induced magnetization motion. IEEE Electron Device Letters, 30(3):294--297, March 2009.Google ScholarCross Ref
- S. Kaya et al. Analysis of statistical fluctuations due to line edge roughness in sub 0.1μm mosfet's. In SISPAD., pages 78--81, 2001.Google Scholar
- S. Yu et al. Full 3d simulation of gate line edge roughness impact on sub-30 nm finfets. Silicon Nanoelectronics Workshop (SNW), 2008.Google Scholar
Recommendations
Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations
ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and designThis paper explores the effectiveness of dual-Vt design under aggressive scaling of technology, which results in significant increase in all components of leakage (subthreshold, gate and junction tunneling) while having large variations in process ...
Device-aware yield-centric dual-Vt design under parameter variations in nanoscale technologies
Dual-Vt design technique has proven to be extremely effective in reducing subthreshold leakage in both active and standby mode of operation of a circuit in submicrometer technologies. However, aggressive scaling of technology results in different ...
Variability-Tolerant Memristor-based Ratioed Logic in Crossbar Array
NANOARCH '18: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale ArchitecturesThe advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this device technology, with several emerging applications including that of logic circuits. Several memristive logic families have ...
Comments