research-article

An energy efficient cache design using spin torque transfer (STT) RAM

Authors:

Sudhakar YalamanchiliAuthors Info & Claims

ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

Pages 389 - 394

https://doi.org/10.1145/1840845.1840931

Published: 18 August 2010 Publication History

Get Access

Abstract

The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technology as a replacement for SRAM based lower level caches - Spin Torque Transfer(STT) RAM. While STTRAM achieves a reduction in leakage energy of 90% compared to SRAM, the dynamic energy for a write operation is 2X that of SRAM. Consequently, we propose additional microarchitectural optimizations to reduce overall dynamic energy which achieve an average reduction in dynamic energy over the base case of 30% with a range of 16% to 60% across 10 benchmarks.

References

[1]

Ramaswamy, S. and Yalamanchili, S. 2008. An utilization driven framework for energy efficient caches. In Proceedings of the 15th international Conference on High Performance Computing (Bangalore, India, December 17 - 20, 2008). P. Sadayappan, M. Parashar, R. Badrinath, and V. K. Prasanna, Eds. Lecture Notes In Computer Science. Springer-Verlag, Berlin, Heidelberg, 583--594.

Digital Library

Google Scholar

[2]

Xiaoxia Wu; Jian Li; Lixin Zhang; Speight, E.; Yuan Xie;, "Power and performance of read-write aware Hybrid Caches with non-volatile memories," Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09., vol., no., pp.737--742, 20--24 April 200.

Digital Library

Google Scholar

[3]

Wu, X., Li, J., Zhang, L., Speight, E., Rajamony, R., and Xie, Y. 2009. Hybrid cache architecture with disparate memory technologies. In Proceedings of the 36th Annual international Symposium on Computer Architecture (Austin, TX, USA, June 20 - 24, 2009). ISCA '09. ACM, New York, NY, 34--45. DOI= http://doi.acm.org/10.1145/1555754.155576.

Digital Library

Google Scholar

[4]

Zhou, P., Zhao, B., Yang, J., and Zhang, Y. 2009. Energy reduction for STT-RAM using early write termination. In Proceedings of the 2009 international Conference on Computer-Aided Design (San Jose, California, November 02 - 05, 2009). ICCAD '09. ACM, New York, NY, 264--268. DOI= http://doi.acm.org/10.1145/1687399.168744.

Digital Library

Google Scholar

[5]

Qureshi, M. K., Srinivasan, V., and Rivers, J. A. 2009. Scalable high performance main memory system using phase-change memory technology. In Proceedings of the 36th Annual international Symposium on Computer Architecture (Austin, TX, USA, June 20 - 24, 2009). ISCA '09. ACM, New York, NY, 24--33. DOI= http://doi.acm.org/10.1145/1555754.155576.

Digital Library

Google Scholar

[6]

Lee, B. C., Ipek, E., Mutlu, O., and Burger, D. 2009. Architecting phase change memory as a scalable dram alternative. In Proceedings of the 36th Annual international Symposium on Computer Architecture (Austin, TX, USA, June 20 - 24, 2009). ISCA '09. ACM, New York, NY, 2--13. DOI= http://doi.acm.org/10.1145/1555754.155575.

Digital Library

Google Scholar

[7]

Hosomi, M.; Yamagishi, H.; Yamamoto, T.; Bessho, K.; Higo, Y.; Yamane, K.; Yamada, H.; Shoji, M.; Hachino, H.; Fukumoto, C.; Nagao, H.; Kano, H.;, "A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram," Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, vol., no., pp.459--462, 5--5 Dec. 200.

Google Scholar

[8]

Leuschner, R.; Klostermann, U.K.; Park, H.; Dahmani, F.; Dittrich, R.; Grigis, C.; Hernan, K.; Mege, S.; Park, C.; Clech, M.C.; Lee, G. Y.; Bournat, S.; Altimime, L.; Mueller, G.;, "Thermal Select MRAM with a 2-bit Cell Capability for beyond 65 nm Technology Node," Electron Devices Meeting, 2006. IEDM '06. International, vol., no., pp. 1--4, 11--13 Dec. 200.

Google Scholar

[9]

Xiangyu Dong; Xiaoxia Wu; Guangyu Sun; Yuan Xie; Li, H.; Yiran Chen;, "Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement," Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, vol., no., pp.554--559, 8--13 June 200.

Digital Library

Google Scholar

[10]

Muralimanohar, N.; Balasubramonian, R.; Jouppi, N.P.;, "Architecting Efficient Interconnects for Large Caches with CACTI 6.0," Micro, IEEE, vol.28, no.1, pp.69--79, Jan.-Feb. 200.

Digital Library

Google Scholar

[11]

Loh, G.H.; Subramaniam, S.; Yuejian Xie;, "Zesto: A cycle-level simulator for highly detailed microarchitecture exploration," Performance Analysis of Systems and Software, 2009. ISPASS 2009. IEEE International Symposium on, vol., no., pp.53--64, 26--28 April 200.

Google Scholar

[12]

McCalpin, John D.: "STREAM: Sustainable Memory Bandwidth in High Performance Computers", a continually updated technical report (1991--2007), available at: "http://www.cs.virginia.edu/stream/".

Google Scholar

[13]

Abella, J., González, A., Vera, X., and O'Boyle, M. F. 2005. IATAC: a smart predictor to turn-off L2 cache lines. ACM Trans. Archit. Code Optim. 2, 1 (Mar. 2005), 55--77. DOI= http://doi.acm.org/10.1145/1061267.1061271.

Digital Library

Google Scholar

Cited By

View all

Bagchi ADharamjeet Rishabh OSuri MPanda P(2024)POEM: Performance Optimization and Endurance Management for Non-volatile CachesACM Transactions on Design Automation of Electronic Systems10.1145/365345229:5(1-36)Online publication date: 27-Mar-2024
https://dl.acm.org/doi/10.1145/3653452
Karunakar SKalayappan R(2024)CaH2:Criticality aware Hybrid L22024 IEEE 31st International Conference on High Performance Computing, Data and Analytics Workshop (HiPCW)10.1109/HiPCW63042.2024.00030(105-106)Online publication date: 18-Dec-2024
https://doi.org/10.1109/HiPCW63042.2024.00030
Singh SSurana NPrasad KJain PMekie JAwasthi M(2023)HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache HierarchyACM Transactions on Architecture and Code Optimization10.1145/357283920:2(1-20)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1145/3572839
Show More Cited By

Index Terms

An energy efficient cache design using spin torque transfer (STT) RAM
1. Hardware
  1. Hardware validation

Recommendations

Efficient STT-RAM last-level-cache architecture to replace DRAM cache
MEMSYS '17: Proceedings of the International Symposium on Memory Systems

Recent research has proposed die-stacked Last Level Cache (LLC) to overcome the Memory Wall. Lately, Spin-Transfer-Torque Random Access Memory (STT-RAM) caches have been recommended as they provide improved energy efficiency compared to DRAM caches. ...
Spin-transfer torque magnetic random access memory (STT-MRAM)
Special issue on memory technologies

Spin-transfer torque magnetic random access memory (STT-MRAM) is a novel, magnetic memory technology that leverages the base platform established by an existing 100+nm node memory product called MRAM to enable a scalable nonvolatile memory solution for ...
Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)

Because of its high storage density with superior scalability, low integration cost and reasonably high access speed, spin-torque transfer random access memory (STT RAM) appears to have a promising potential to replace SRAM as last-level on-chip cache (...

Comments

Information & Contributors

Information

Published In

ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

August 2010

458 pages

ISBN:9781450301466

DOI:10.1145/1840845

General Chairs:
Vojin Oklobdzija
University of Texas, Dallas
,
Barry Pangle
Mentor Graphics
,
Naehyuck Chang
Seoul National University
,
Program Chairs:
Naresh Shanbhag
University of Illinois at Urbana-Champaign
,
Chris H. Kim
University of Minnesota

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

IEEE CAS

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 August 2010

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ISLPED'10

Sponsor:

SIGDA

ISLPED'10: International Symposium on Low Power Electronics and Design

August 18 - 20, 2010

Texas, Austin, USA

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

95
Total Citations
View Citations
678
Total Downloads

Downloads (Last 12 months)10
Downloads (Last 6 weeks)1

Reflects downloads up to 02 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Bagchi ADharamjeet Rishabh OSuri MPanda P(2024)POEM: Performance Optimization and Endurance Management for Non-volatile CachesACM Transactions on Design Automation of Electronic Systems10.1145/365345229:5(1-36)Online publication date: 27-Mar-2024
https://dl.acm.org/doi/10.1145/3653452
Karunakar SKalayappan R(2024)CaH2:Criticality aware Hybrid L22024 IEEE 31st International Conference on High Performance Computing, Data and Analytics Workshop (HiPCW)10.1109/HiPCW63042.2024.00030(105-106)Online publication date: 18-Dec-2024
https://doi.org/10.1109/HiPCW63042.2024.00030
Singh SSurana NPrasad KJain PMekie JAwasthi M(2023)HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache HierarchyACM Transactions on Architecture and Code Optimization10.1145/357283920:2(1-20)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1145/3572839
Inci AIsgenc MMarculescu D(2023)Efficient Deep Learning Using Non-volatile Memory Technology in GPU ArchitecturesEmbedded Machine Learning for Cyber-Physical, IoT, and Edge Computing10.1007/978-3-031-19568-6_8(225-252)Online publication date: 1-Oct-2023
https://doi.org/10.1007/978-3-031-19568-6_8
Yang YChen SChang Y(2022)Evolving Skyrmion Racetrack Memory as Energy-Efficient Last-Level Cache DevicesProceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design10.1145/3531437.3539709(1-6)Online publication date: 1-Aug-2022
https://dl.acm.org/doi/10.1145/3531437.3539709
Inci AIsgenc MMarculescu D(2022)DeepNVM++: Cross-Layer Modeling and Optimization Framework of Nonvolatile Memories for Deep LearningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312714841:10(3426-3437)Online publication date: Oct-2022
https://doi.org/10.1109/TCAD.2021.3127148
Khan MGhosh S(2021)Comprehensive Study of Security and Privacy of Emerging Non-Volatile MemoriesJournal of Low Power Electronics and Applications10.3390/jlpea1104003611:4(36)Online publication date: 24-Sep-2021
https://doi.org/10.3390/jlpea11040036
Liu CChen LHao XNi M(2021)Optimized fast data migration for hybrid DRAM/STT-MRAM main memoryIEICE Electronics Express10.1587/elex.18.20210493Online publication date: 2021
https://doi.org/10.1587/elex.18.20210493
Shen FXu CZhang JChen YHe Y(2021)Reinforcement Learning based Data Compression for Energy-Efficient Non-volatile Caches2021 IEEE 23rd Int Conf on High Performance Computing & Communications; 7th Int Conf on Data Science & Systems; 19th Int Conf on Smart City; 7th Int Conf on Dependability in Sensor, Cloud & Big Data Systems & Application (HPCC/DSS/SmartCity/DependSys)10.1109/HPCC-DSS-SmartCity-DependSys53884.2021.00110(662-668)Online publication date: Dec-2021
https://doi.org/10.1109/HPCC-DSS-SmartCity-DependSys53884.2021.00110
Kitagata DYamamoto SSugahara S(2020)Proactive useless data flush architecture for nonvolatile SRAM using magnetic tunnel junctionsIEICE Electronics Express10.1587/elex.17.20200032Online publication date: 2020
https://doi.org/10.1587/elex.17.20200032
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Efficient STT-RAM last-level-cache architecture to replace DRAM cache

Spin-transfer torque magnetic random access memory (STT-MRAM)

Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)

Comments

Information

Published In

Sponsors

In-Cooperation

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations