skip to main content
10.1145/1950413.1950442acmconferencesArticle/Chapter ViewAbstractPublication PagesfpgaConference Proceedingsconference-collections
research-article

Line-level incremental resynthesis techniques for FPGAs

Published: 27 February 2011 Publication History

Abstract

FPGA logic density is roughly doubling at every process generation. Consequently, it is becoming increasingly challenging for FPGA CAD tools to keep up with the growing complexities of high-speed designs while keeping CAD run-times reasonable. In this paper, we present a novel incremental resynthesis tool called Line-Level Incremental reSynthesis (LLIS), integrated within an industrial tool suite, that addresses the problems of timing closure as well as CAD runtime (patent pending). We describe a general framework that can incrementally reuse results from a previous compile based on automatic differencing of HDL changes. We show that it is possible to reduce synthesis runtime by 6.5x for common HDL changes. As compared with complete resynthesis, we preserve known good timing solutions more than 82% of the time. This represents a 3X improvement vs. non-incremental techniques.

References

[1]
Altera. Quartus II Handbook v9.0, 2009.
[2]
Altera. Stratix IV Device Handbook. v3.3, Jun. 2009.
[3]
D. Brand, A. Drumm, S. Kundu, P. Narain, Incremental synthesis, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.14--18, November 1994.
[4]
D. Chen, D. Singh, Parallelizing FPGA Technology Mapping using Graphics Processing Units (GPUs), Proceedings of the international conference on Field Programmable Logic and Applications, September 2010.
[5]
A. Choong, R. Beidas, J. Zhu, Parallelizing Simulated Annealing-Based Placement Using GPGPU, Proceedings of the international conference on Field Programmable Logic and Applications, September 2010.
[6]
P. Chung, I. Hajj, ACCORD Automatic Catching and CORrection of Logic Design Errors in Combinational Circuits, Proc. of International Test Conference, September 1992.
[7]
A. Jayalakshmi, Auto ECO Flow Development for Functional ECO Using Efficient Error Rectification Method Based on FV Tool, Proceedings of the 38th ACM/IEEE conference on Design automation, 2009.
[8]
S. Krishnaswamy, H. Ren, N. Modi, R. Puri, DeltaSyn: An Efficient Logic Difference Optimizer for ECO Synthesis, Proceedings of the International Conference on Computer Aided Design, November 2009.
[9]
Y. Kukimoto, M. Fujita, Rectification method for lookup-table type FPGA's, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.54--61, November 1992.
[10]
C. Lin, Y. Huang, S. Chang, W. Jone, Design and design automation of rectification logic for engineering change, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18--21, 2005.
[11]
A. Ling, S. Brown, J. Zhu, S. Safarpour, Towards automated ECOs in FPGAs, Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, February 2009.
[12]
A. Ludwin, V. Betz, K. Padalia, High-quality, deterministic parallel placement for FPGAs on commodity hardware, Proceedings of the international ACM/SIGDA symposium on Field programmable gate arrays, February 2008.
[13]
J. Madre, O. Coudert, J. Billon, Automating the Diagnosis and the Rectification of Design Errors with PRIAMÎ, Proc. of ICCAD, November 1989, pp.30--33.
[14]
I. Pomeranz, S. Reddy, On Diagnosis and Correction of Design Errors, Proc. of ICCAD, November 1993.
[15]
T. Shinsha, T. Kubo, Y. Sakataya, J. Koshishita, K. Ishihara, Incremental logic synthesis through gate logic structure identification, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.391--397, July 1986.
[16]
Y. Sankar, J. Rose, Trading quality for compile time: ultra-fast placement for FPGAs, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.157--166, February 1999.
[17]
D. Singh, V. Manohararajah, S. D. Brown, Two-Stage Physical Synthesis for FPGAs, Proceedings of the IEEE Custom Integrated Circuits Conference, p.171--178, Sept 2005.
[18]
G. Swamy, S. Rajamani, C. Lennard, R. Brayton, Minimal logic re-synthesis forengineering change, International Symposium on Circuits and Systems, 1997.
[19]
J. Swartz, V. Betz, J. Rose, A fast routability-driven router for FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.140--149, February 1998.
[20]
R. Tessier, Fast placement approaches for FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.2, p.284--305, April 2002.

Cited By

View all

Index Terms

  1. Line-level incremental resynthesis techniques for FPGAs

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    FPGA '11: Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
    February 2011
    300 pages
    ISBN:9781450305549
    DOI:10.1145/1950413
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 27 February 2011

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tag

    1. algorithms

    Qualifiers

    • Research-article

    Conference

    FPGA '11
    Sponsor:

    Acceptance Rates

    Overall Acceptance Rate 125 of 627 submissions, 20%

    Upcoming Conference

    FPGA '25

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)17
    • Downloads (Last 6 weeks)5
    Reflects downloads up to 20 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2019)SMatchProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317912(1-6)Online publication date: 2-Jun-2019
    • (2017)LiveSynthProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062275(1-6)Online publication date: 18-Jun-2017
    • (2016)FPGA Synthesis and Physical DesignElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-18(373-413)Online publication date: 14-Apr-2016
    • (2013)Maximizing speed and density of tiled FPGA overlays via partitioning2013 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2013.6718360(238-245)Online publication date: Dec-2013

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media