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Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis

Published: 27 March 2011 Publication History

Abstract

A novel clock mesh network synthesis approach is proposed in this paper which generates an improved mesh size with registers placed incrementally considering the timing slack on the data paths and the non-uniform grid wire placement. The primary objective of the method is to reduce the power dissipation without a global skew degradation, which is achieved through a sparse and non-uniform mesh implementation with registers incrementally placed in close vicinity to the mesh grids. The incremental register placement is based on the timing information in order to preserve the timing slack of the circuit. Experimental results show that the total wirelength (mesh grid wires and stub wires) as well as the power dissipation is reduced significantly on the clock mesh network. Specifically, the wirelength of the mesh network and the power dissipation of the clock network are reduced by 52% and 48% on average, respectively. Moreover, the global clock skew and the non-negative timing slack are preserved.

References

[1]
NEOS Solvers. http://neos.mcs.anl.gov/neos/solvers/.
[2]
A. Abdelhadi, R. Ginosar, A. Kolodny, and E. G. Friedman. Timing-driven variation-aware nonuniform clock mesh synthesis. In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), pages 15--20, May 2010.
[3]
R. Chaturvedi and J. Hu. An efficient merging scheme for prescribed skew clock routing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(6):750--754, June 2005.
[4]
W.-K. Chen, editor. The VLSI Handbook. CRC Press, 1st edition, 1999.
[5]
Y. Chen and D. F. Wong. An algorithm for zero-skew clock tree routing with buffer insertion. In Proceedings of the European Conference on Design and Test (ED&TC), pages 230--236, March 1996.
[6]
J. Cong, A. B. Kahng, C.-K. Koh, and C.-W. Tsao. Bounded-skew clock and steiner routing. ACM Transactions on Design Automation of Electronic Systems (TODAES), 3(3):341--388, 1998.
[7]
T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein. Introduction to Algorithms. MIT Press, 2nd edition, 2001.
[8]
W. Elmore. The transient response of damped linear networks with particular regard to wideband amplifiers. Journal of Applied Physics (AIP), 19(1):55--63, January 1948.
[9]
E. G. Friedman. Clock Distribution Networks in VLSI Circuits and Systems. IEEE Press, 1995.
[10]
M. R. Guthaus, G. Wilke, and R. Reis. Non-uniform clock mesh optimization with linear programming buffer insertion. In Proceedings of the ACM/IEEE Design Automation Conference (DAC), pages 74--79, June 2010.
[11]
N. Kurd, J. Barkarullah, R. Dizon, T. Fletcher, and P. Madland. A multigigahertz clocking scheme for the pentium(r) 4 microprocessor. IEEE Journal of Solid-State Circuits (JSSC), 36(11):1647--1653, Nov. 2001.
[12]
A. Rajaram, J. Hu, and R. Mahapatra. Reducing clock skew variability via cross links. In Proceedings of the ACM/IEEE Design Automation Conference (DAC), pages 18--23, June 2004.
[13]
A. Rajaram and D. Pan. Meshworks: An efficient framework for planning, synthesis and optimization of clock mesh networks. In Asia and South Pacific Design Automation Conference (ASPDAC), pages 250--257, Jan. 2008.
[14]
A. Rajaram and D. Z. Pan. Variation tolerant buffered clock network synthesis with cross links. In Proceedings of the International Symposium on Physical Design (ISPD), pages 157--164, 2006.
[15]
A. Rajaram, D. Z. Pan, and J. Hu. Improved algorithms for link-based non-tree clock networks for skew variability reduction. In Proceedings of the International Symposium on Physical Design (ISPD), pages 55--62, 2005.
[16]
P. Restle, C. Carter, J. Eckhardt, B. Krauter, B. McCredie, K. Jenkins, A. Weger, and A. Mule. The clock distribution of the power4 microprocessor. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), volume 1, pages 144--145, Feb. 2002.
[17]
P. Restle, T. McNamara, D. Webber, P. Camporese, K. Eng, K. Jenkins, D. Allen, M. Rohn, M. Quaranta, D. Boerstler, C. Alpert, C. Carter, R. Bailey, J. Petrovick, B. Krauter, and B. McCredie. A clock distribution network for microprocessors. IEEE Journal of Solid-State Circuits (JSSC), 36(5):792--799, May 2001.
[18]
R. S. Shelar. An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors. In Proceedings of the International Symposium on Physical Design (ISPD), pages 141--148, Mar. 2009.
[19]
C. N. Sze. Ispd 2010 high performance clock network synthesis contest: benchmark suite and results. In Proceedings of the International Symposium on Physical Design (ISPD), pages 143--143, 2010.
[20]
S. Tam, J. Leung, R. Limaye, S. Choy, S. Vora, and M. Adachi. Clock generation and distribution of a dual-core xeon processor with 16mb l3 cache. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), pages 1512--1521, Feb. 2006.
[21]
B. Taskin and I. S. Kourtev. Delay insertion method in clock skew scheduling. In Proceedings of the International Symposium on Physical Design (ISPD), pages 47--54, April 2005.
[22]
G. Venkataraman, Z. Feng, J. Hu, and P. Li. Combinatorial algorithms for fast clock mesh optimization. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 18(1):131--141, Jan. 2010.
[23]
T. Xanthopoulos, D. Bailey, A. Gangwar, M. Gowan, A. Jain, and B. Prewitt. The design and analysis of the clock distribution network for a 1.2 ghz alpha microprocessor. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), pages 402--403, Feb. 2001.

Cited By

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  • (2024)Clock mesh synthesis through dynamic programming with physical parameters considerationIntegration10.1016/j.vlsi.2024.102261(102261)Online publication date: Aug-2024
  • (2014)Clock Mesh Network Design with Through-Silicon Vias in 3D Integrated CircuitsETRI Journal10.4218/etrij.14.0113.125736:6(931-941)Online publication date: 1-Dec-2014
  • (2012)Integrated Clock Mesh Synthesis With Incremental Register PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.217349131:2(217-227)Online publication date: 1-Feb-2012
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    cover image ACM Conferences
    ISPD '11: Proceedings of the 2011 international symposium on Physical design
    March 2011
    192 pages
    ISBN:9781450305501
    DOI:10.1145/1960397
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 27 March 2011

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    Author Tags

    1. clock mesh
    2. clock network
    3. physical design
    4. register placement
    5. vlsi cad

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    March 27 - 30, 2011
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    Cited By

    View all
    • (2024)Clock mesh synthesis through dynamic programming with physical parameters considerationIntegration10.1016/j.vlsi.2024.102261(102261)Online publication date: Aug-2024
    • (2014)Clock Mesh Network Design with Through-Silicon Vias in 3D Integrated CircuitsETRI Journal10.4218/etrij.14.0113.125736:6(931-941)Online publication date: 1-Dec-2014
    • (2012)Integrated Clock Mesh Synthesis With Incremental Register PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.217349131:2(217-227)Online publication date: 1-Feb-2012
    • (2012)Multi-voltage domain clock mesh designProceedings of the 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)10.1109/ICCD.2012.6378641(201-206)Online publication date: 30-Sep-2012

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