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A framework for dynamically instrumenting GPU compute applications within GPU Ocelot

Published: 05 March 2011 Publication History

Abstract

In this paper we present the design and implementation of a dynamic instrumentation infrastructure for PTX programs that procedurally transforms kernels and manages related data structures. We show how performing instrumentation within the GPU Ocelot dynamic compiler infrastructure provides unique capabilities not available to other profiling and instrumentation toolchains for GPU computing. We demonstrate the utility of this instrumentation capability with three example scenarios - (1) performing workload characterization accelerated by a GPU, (2) providing load imbalance information for use by a resource allocator, and (3) providing compute utilization feedback to be used online by a simulated process scheduler that might be found in a hypervisor. Additionally, we measure both (1) the compilation overheads of performing dynamic compilation and (2) the increases in runtimes when executing instrumented kernels. On average, compilation overheads due to instrumentation consisted of 69% of the time needed to parse a kernel module, in the case of the Parboil benchmark suite. Slowdowns for instrumenting each basic block ranged from 1.5x to 5.5x, with the largest slowdowns attributed to kernels with large numbers of short, compute-bound blocks.

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cover image ACM Other conferences
GPGPU-4: Proceedings of the Fourth Workshop on General Purpose Processing on Graphics Processing Units
March 2011
101 pages
ISBN:9781450305693
DOI:10.1145/1964179
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 05 March 2011

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Author Tags

  1. CUDA
  2. GPGPU
  3. GPU computing
  4. Ocelot
  5. OpenCL
  6. PTX
  7. Parboil
  8. Rodinia
  9. dynamic binary compilation
  10. instrumentation

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GPGPU-4

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Overall Acceptance Rate 57 of 129 submissions, 44%

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  • (2023)TB-TBP: a task-based adaptive routing algorithm for network-on-chip in heterogenous CPU-GPU architecturesThe Journal of Supercomputing10.1007/s11227-023-05700-780:5(6311-6335)Online publication date: 23-Oct-2023
  • (2022)NaviSimProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1145/3559009.3569666(333-345)Online publication date: 8-Oct-2022
  • (2022)CRONUS: Fault-isolated, Secure and High-performance Heterogeneous Computing for Trusted Execution Environment2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00019(124-143)Online publication date: Oct-2022
  • (2021)LocalityGuru: A PTX Analyzer for Extracting Thread Block-level Locality in GPGPUs2021 IEEE International Conference on Networking, Architecture and Storage (NAS)10.1109/NAS51552.2021.9605411(1-8)Online publication date: Oct-2021
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  • (2021)Did the GPU obfuscate the load imbalance in my MPI simulation?2021 IEEE/ACM International Workshop on Hierarchical Parallelism for Exascale Computing (HiPar)10.1109/HiPar54615.2021.00008(20-29)Online publication date: Nov-2021
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  • (2019)CUDA Flux: A Lightweight Instruction Profiler for CUDA Applications2019 IEEE/ACM Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS)10.1109/PMBS49563.2019.00014(73-81)Online publication date: Nov-2019
  • (2018)Efficient Cache Performance Modeling in GPUs Using Reuse Distance AnalysisACM Transactions on Architecture and Code Optimization10.1145/329105115:4(1-24)Online publication date: 19-Dec-2018
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