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View all- Mangiras DChinnery DDimitrakopoulos G(2023)Task-Based Parallel Programming for Gate SizingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319749042:4(1309-1322)Online publication date: 1-Apr-2023
- Sharma AChinnery DReimann TBhardwaj SChu C(2019)Fast Lagrangian Relaxation Based Multi-Threaded Gate Sizing Using Simple Timing CalibrationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.2915324(1-1)Online publication date: 2019
- Sharma AChinnery DBhardwaj SChu CMarculescu DLiu F(2015)Fast Lagrangian Relaxation Based Gate Sizing using Multi-ThreadingProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840879(426-433)Online publication date: 2-Nov-2015
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