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GPU-Based Parallelization for Fast Circuit Optimization

Published: 01 June 2011 Publication History

Abstract

The progress of GPU (Graphics Processing Unit) technology opens a new avenue for boosting computing power. This work is an attempt to exploit the GPU for accelerating VLSI circuit optimization. We propose GPU-based parallel computing techniques and apply them on simultaneous gate sizing and threshold voltage assignment, which is a popular method for VLSI performance and power optimization. These techniques include efficient task scheduling and memory organization, all of which are aimed to fully utilize the advantages of GPUs. Compared to conventional sequential computation, our techniques can provide up to 56× (39× on average) speedup without any sacrifice on solution quality.

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Cited By

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  • (2023)Task-Based Parallel Programming for Gate SizingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319749042:4(1309-1322)Online publication date: 1-Apr-2023
  • (2019)Fast Lagrangian Relaxation Based Multi-Threaded Gate Sizing Using Simple Timing CalibrationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.2915324(1-1)Online publication date: 2019
  • (2015)Fast Lagrangian Relaxation Based Gate Sizing using Multi-ThreadingProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840879(426-433)Online publication date: 2-Nov-2015
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Published In

cover image ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems  Volume 16, Issue 3
June 2011
330 pages
ISSN:1084-4309
EISSN:1557-7309
DOI:10.1145/1970353
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 June 2011
Accepted: 01 December 2010
Revised: 01 August 2010
Received: 01 January 2010
Published in TODAES Volume 16, Issue 3

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Author Tags

  1. Circuit optimization
  2. General-Purpose Graphics Computing Unit (GPGPU)
  3. parallelization

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Cited By

View all
  • (2023)Task-Based Parallel Programming for Gate SizingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319749042:4(1309-1322)Online publication date: 1-Apr-2023
  • (2019)Fast Lagrangian Relaxation Based Multi-Threaded Gate Sizing Using Simple Timing CalibrationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.2915324(1-1)Online publication date: 2019
  • (2015)Fast Lagrangian Relaxation Based Gate Sizing using Multi-ThreadingProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840879(426-433)Online publication date: 2-Nov-2015
  • (2015)Detection of illegitimate access to JTAG via statistical learning in chipProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755777(109-114)Online publication date: 9-Mar-2015
  • (2015)Fast Lagrangian Relaxation based gate sizing using multi-threading2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2015.7372601(426-433)Online publication date: Nov-2015
  • (2015)Toward GPU-accelerated Database OptimizationDatenbank-Spektrum10.1007/s13222-015-0184-315:2(131-140)Online publication date: 21-Apr-2015
  • (2013)A novel differential scan attack on advanced DFT structuresACM Transactions on Design Automation of Electronic Systems10.1145/250501418:4(1-22)Online publication date: 25-Oct-2013
  • (2012)Passive imaging of moving targets exploiting multiple scattering using sparse distributed aperturesInverse Problems10.1088/0266-5611/28/12/12500928:12(125009)Online publication date: 19-Nov-2012

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