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invited-talk

Memory systems in the many-core era: challenges, opportunities, and solution directions

Published: 04 June 2011 Publication History

Abstract

The memory subsystem is a fundamental performance and energy bottleneck in almost all computing systems. Recent trends towards increasingly more cores on die, consolidation of diverse workloads on a single chip, and difficulty of DRAM scaling impose new requirements and exacerbate old demands on the memory system. In particular, the need for memory bandwidth and capacity is increasing [14], applications' interference in memory system increasingly limits system performance and makes the system hard to control [12], memory energy and power are key design concerns [8], and DRAM technology consumes significant amount of energy and does not scale down easily to smaller technology nodes [7]. Fortunately, some promising solution directions exist.
In this talk, we will examine recent technology, application, and architecture trends motivating a fundamental rethinking of the memory hierarchy. Based on this motivation, we will describe requirements from an ideal memory system suitable for the many-core era. The talk will examine questions one would need to answer in approximating the ideal memory system and possible avenues that seem promising for the research community to explore. In particular, we will focus on the problem of uncontrolled inter-application interference in the memory system and draw upon our experiences in solving it by designing quality-of-service (QoS) aware memory controllers [5, 6, 9, 10, 11, 12], interconnects [1 2 13], and entire memory systems. We will make a case forapplication- and QoS-aware design of memory systems and [3, 4]integrated/cooperative design of cores, interconnects, and memory components to optimize the overall system.

References

[1]
R. Das, O. Mutlu, T. Moscibroda, and C. Das. Application-aware prioritization mechanisms for on-chip networks. In International Symposium on Microarchitecture (MICRO-42), 2009.
[2]
R. Das, O. Mutlu, T. Moscibroda, and C. Das. Aergia: Exploiting packet latency slack in on-chip networks. In International Symposium on Computer Architecture (ISCA-37), 2010.
[3]
E. Ebrahimi, C. J. Lee, O. Mutlu, and Y. N. Patt. Fairness via source throttling: A configurable and high-performance fairness substrate for multi-core memory systems. In International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XV), 2010.
[4]
E. Ebrahimi, C. J. Lee, O. Mutlu, and Y. N. Patt. Prefetch-aware shared resource management for multi-core systems. In International Symposium on Computer Architecture (ISCA-38), 2011.
[5]
Y. Kim, D. Han, O. Mutlu, and M. Harchol-Balter. ATLAS: a scalable and high-performance scheduling algorithm for multiple memory controllers. In International Symposium on High-Performance Computer Architecture (HPCA-16), 2010.
[6]
Kim, Papamichael, Mutlu, and Harchol-Balter}tcm-micro10Y. Kim, M. Papamichael, O. Mutlu, and M. Harchol-Balter. Thread cluster memory scheduling: Exploiting differences in memory access behavior. In International Symposium on Microarchitecture (MICRO-43), 2010
[7]
B. C. Lee, E. Ipek, O. Mutlu, and D. Burger. Architecting phase change memory as a scalable DRAM alternative. In International Symposium on Computer Architecture (ISCA-36), 2009.
[8]
C. Lefurgy, K. Rajamani, F. L. Rawson-III, W. M. Felter, M. Kistler, and T. W. Keller. Energy management for commercial servers. IEEE Computer, 36 (12): 39--48, 2003.
[9]
T. Moscibroda and O. Mutlu. Memory performance attacks: Denial of memory service in multi-core systems. In 16th USENIX Security Symposium, 2007.
[10]
T. Moscibroda and O. Mutlu. Distributed order scheduling and its application to multi-core DRAM controllers. In ACM Symposium on Principles of Distributed Computing (PODC-27), 2008.
[11]
O. Mutlu and T. Moscibroda. Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems. In International Symposium on Computer Architecture (ISCA-35), 2008.
[12]
O. Mutlu and T. Moscibroda. Stall-time fair memory access scheduling for chip multiprocessors. In International Symposium on Microarchitecture (MICRO-40), 2007.
[13]
G. Nychis, C. Fallin, T. Moscibroda, and O. Mutlu. Next generation on-chip networks: What kind of congestion control do we need? In 9th ACM Workshop on Hot Topics in Networks (HOTNETS), 2010.
[14]
M. K. Qureshi, V. Srinivasan, and J. A. Rivers. Scalable high performance main memory system using phase-change memory technology. In International Symposium on Computer Architecture (ISCA-36), 2009.

Cited By

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  • (2015)A Survey of Phase Change Memory SystemsJournal of Computer Science and Technology10.1007/s11390-015-1509-230:1(121-144)Online publication date: 21-Jan-2015
  • (2015)Main Memory Scaling: Challenges and Solution DirectionsMore than Moore Technologies for Next Generation Computer Design10.1007/978-1-4939-2163-8_6(127-153)Online publication date: 21-Jan-2015
  • (2014)On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed cachesACM Transactions on Embedded Computing Systems10.1145/256793113:3s(1-21)Online publication date: 28-Mar-2014
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  1. Memory systems in the many-core era: challenges, opportunities, and solution directions

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    Published In

    cover image ACM SIGPLAN Notices
    ACM SIGPLAN Notices  Volume 46, Issue 11
    ISMM '11
    November 2011
    135 pages
    ISSN:0362-1340
    EISSN:1558-1160
    DOI:10.1145/2076022
    Issue’s Table of Contents
    • cover image ACM Conferences
      ISMM '11: Proceedings of the international symposium on Memory management
      June 2011
      148 pages
      ISBN:9781450302630
      DOI:10.1145/1993478

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 04 June 2011
    Published in SIGPLAN Volume 46, Issue 11

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    Author Tags

    1. chip multiprocessors
    2. interconnects
    3. memory systems
    4. multi-core
    5. quality of service

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    Cited By

    View all
    • (2015)A Survey of Phase Change Memory SystemsJournal of Computer Science and Technology10.1007/s11390-015-1509-230:1(121-144)Online publication date: 21-Jan-2015
    • (2015)Main Memory Scaling: Challenges and Solution DirectionsMore than Moore Technologies for Next Generation Computer Design10.1007/978-1-4939-2163-8_6(127-153)Online publication date: 21-Jan-2015
    • (2014)On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed cachesACM Transactions on Embedded Computing Systems10.1145/256793113:3s(1-21)Online publication date: 28-Mar-2014
    • (2015)Main Memory Scaling: Challenges and Solution DirectionsMore than Moore Technologies for Next Generation Computer Design10.1007/978-1-4939-2163-8_6(127-153)Online publication date: 21-Jan-2015
    • (2014)Research Problems and Opportunities in Memory SystemsSupercomputing Frontiers and Innovations: an International Journal10.14529/jsfi1403021:3(19-55)Online publication date: 12-Oct-2014
    • (2014)Memory SystemsComputing Handbook, Third Edition10.1201/b16812-22(1-22)Online publication date: 8-May-2014
    • (2014)HiTSProceedings of the 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing10.1109/SBAC-PAD.2014.36(206-213)Online publication date: 22-Oct-2014
    • (2013)Memory scaling: A systems architecture perspective2013 5th IEEE International Memory Workshop10.1109/IMW.2013.6582088(21-25)Online publication date: May-2013

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