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Poster: revisiting virtual channel memory for performance and fairness on multi-core architecture

Published: 31 May 2011 Publication History

Abstract

In modern multi-core chip architecture, the DRAM system is shared by more and more cores and high bandwidth I/O devices. This trend would make the problem of request contention and un-fairness more serious. Previous research focused on memory sche-duling mechanisms to efficiently and fairly serve memory requests generated by multiple cores. However, the performance is mod-erately improved due to the limited bank-level parallelism in preva-lent DRAM chips. Based on the observation that virtual channel memory (VCM) provides more opportunities for exploiting MLP because it has more channel buffers than banks in conventional DRAM chip, we evaluate VCM technology as an alternative to DRAM for addressing the issues of contention, unfairness and MLP. In this work we implement VCM and leverage the state of art scheduling mechanism on a multi-core architecture. The experi-mental results show that (i) VCM with 32 channels improves ho-mogeneous workloads' IPC by 2.08X on a 16-core system compared to the system with conventional DRAM chips, causing extra area cost by 0.5%, and dynamic and background power pe-nalties by only 5.8% and 0.03% respectively. (ii) For heterogene-ous workloads, VCM significantly reduces unfairness by 82.0% as well as improves the workloads' performance by 1.86X in term of system throughput.

References

[1]
Y. Kim, D. Han, O. Mutlu, and M. Harchol-Balter. ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers. in Proceedings of the 16th International Symposium on High-Performance Computer Architecture (HPCA). 2010.
[2]
O. Mutlu and T. Moscibroda, Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems, in Proceedings of the 35th Annual International Symposium on Computer Architecture, 2008.
[3]
Nec, 64M-bit Virtual Channel SDRAM data sheet, 1998.
[4]
S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens. Memory Access Scheduling. in Proceedings of the 27th annual international symposium on Computer architecture. 2000.

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    Published In

    cover image ACM Conferences
    ICS '11: Proceedings of the international conference on Supercomputing
    May 2011
    398 pages
    ISBN:9781450301022
    DOI:10.1145/1995896

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 31 May 2011

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    Author Tags

    1. mlp
    2. multi-core architecture
    3. qos
    4. shared dram system
    5. unfairness
    6. virtual channel memory

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    ICS '11
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    ICS '11: International Conference on Supercomputing
    May 31 - June 4, 2011
    Arizona, Tucson, USA

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    Overall Acceptance Rate 629 of 2,180 submissions, 29%

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    • (2017)Data Collection Strategy in Low Duty Cycle Wireless Sensor Networks with Mobile SinkInternational Journal of Communications, Network and System Sciences10.4236/ijcns.2017.105B02310:05(227-239)Online publication date: 2017

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