ABSTRACT
Recent advances in Field-Programmable Gate Arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improvements in Computer-Aided Design (CAD) tools, mainly in synthesis tools, greatly simplify the design of large circuits. The RPM (Rapid Prototype Engine for Multiprocessors) Project leverages these two technological advances. Its goal is to develop a common hardware platform for the emulation of multiprocessor systems with different architectures.
For cost reasons, the use of FPGAs in RPM is limited to the memory controllers, while the rest of the emulator, including the processors, memories and interconnect, is built with off-the-shelf components. A flexible non-intrusive event logging mechanism is included at all levels of the memory hierarchy, making it possible to monitor the emulation in very fine detail. This paper presents the hardware design of RPM.
- 1.Aptix Inc., Data Book, Aptix, San Jose, 1993.Google Scholar
- 2.Barroso, L., Iman, S., Jeong, J., Oner, K., Ramamurthy, K., and Dubois, M., "RPM: A Rapid Prototyping Engine for Multiprocessor Systems", IEEE Computer, February 1995. Google ScholarDigital Library
- 3.Catanzaro, B., Multiprecesser System Architectures. Prentice-Hall, 1994. Google ScholarDigital Library
- 4.Jaswinder Pal Singh, Wolf-Dietrich Weber, and Anoop Gupta, "SPLASH: Stanford parallel applications for sharedmemory", Technical Report CSL-TR-91-469, Stanford Computer Systems Laboratory, April 1991. Google ScholarDigital Library
- 5.Dubois, M., Scheurich, C., and Briggs, F.A., "Synchronization, Coherence, and Event Ordering in Multiprocessors," IEEE Computer, Vol. 21, No. 2, pp. 9-21, February 1988. Google ScholarDigital Library
- 6.Hagersten, E., Landin, A., and Haridi, S., "DDM -- A Cache-Only Memory Architecture," IEEE Computer, Vol. 25, No. 9, pp. 44-54, September 1992. Google ScholarDigital Library
- 7.INCA, "VA-II Logic Emulator", INCA, Berkshire, United Kingdom, 1993.Google Scholar
- 8.Ko, B. and Maholtra, L., "Logic Emulation for System- Level Design", Prec. Electro, 1992.Google Scholar
- 9.Lenoski, D., Laudon, J., Gharachorloo, K., Weber, W.- D., Gupta, A., Hennessy, J., Horowitz, M., and Lam, M.S., "The Stanford DASH Multiprocessor," IEEE Computer, pp. 63-79, Vol. 25, No. 3, March 1992. Google ScholarDigital Library
- 10.Li, K. and Hudak, P., "Memory Coherence in Shared Virtual Memory Systems," ACM Transactions on Computer Systems, Vol. 7, No. 4, pp. 321-359, November 1989. Google ScholarDigital Library
- 11.Maliniak, L., "Logic Emulation Meets the Demands of CPU Designers", Electronic Design, vol. 41, no. 7, pp. 36- 40, 1993.Google Scholar
- 12.Stenstrom, P.,"A Survey of Cache Coherence Schemes for Multiprocessors," IEEE Computer, Vol. 23, No. 6, pp. 12-24, June 1990. Google ScholarDigital Library
- 13.Trimberger, S.,"A Reprogrammable Gate Array and Applications," Proceedings of the IEEE, Vol. 81, No. 7, pp. 1030-1041, July 1993.Google ScholarCross Ref
- 14.Walters, S., "Reprogrammable Hardware Emulation Automates System Level ASIC Validation," Prec. WESCON, 199011Google Scholar
Index Terms
- The design of RPM: an FPGA-based multiprocessor emulator
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