Analog design synthesis method using simulated annealing and particle swarm optimization

ABSTRACT

This paper presents a method for analog design synthesis at circuit-level and pareto front exploration of the design through a combined approach of Simulated Annealing (SA) and Particle Swarm Optimization (PSO). The method consists of dividing the design parameters search in three main parts. The first has the objective of finding the minimal specifications defined by the user through the use of SA and using an aggregate objective function to combine all the design objectives into a single cost function. The second part starts when all the minimal specs are met and it performs a single-objective optimization for each objective in order to obtain a non-exhaustive exploration of the pareto front. The third part applies PSO for multiple objective in order to spread the results and find a more accurate pareto front of the design. This approach allows the designer to have a visual feedback about the trade-offs of the design to a specific topology and technology selection. Results of a folded-cascode opamp circuit-level synthesis using a 0.35 μm technology show this method provides a fast approach to good solutions using SA (considering Gain, UGF, Slew Rate, Consumption, Phase Margin, ICMR, Output Swing and PSRR specifications) and further good pareto front exploration through its connection with the PSO algorithm.

References

1. S. Balkir, G. Dundar, and A. S. Ogrenci, Analog VLSI Design Automation. CRC Press, 2003.
2. M. G. Degrauwe, N. Olivier, and E. Dijkstra, "Idac: An iteractive design tool for analog cmos circuits," IEEE Journal of Solid-State Circuits, 1987.
3. V. der Plas, G. Debysyer, G. Leyn, F. Lampaert, K. Vandenbussche, J. Gielen, G. Sansen, W. Veselinovic, and D. P. Leenarts, "Amgie-a synthesis environment for cmos analog integrated circuits," IEEE TCAD, 1037, 2001.
4. G. Yu and P. Li, "Hierarchical analog/mixed-signal circuit optimization under process variations and tuning," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, p. 313, 2011.
5. T. O. Weber and W. A. M. V. Noije, "Text from author removed due to blind issues," 2nd IEEE Latin American Symposium on Circuits and Systems, 2011.
6. M. Reyes-Sierra and C. A. C. Coello, "Multi-objective particle swarm optimizers: A survey of the state-of-the-art," International Journal of Computational Intelligence Research, vol. 2, pp. 287--308, 2006.
7. B. Suman, "Study of simulated annealing based algorithms for multiobjective optimization of a constrained problem," Computers and Chemical Engineering, April 2004.
8. L. C. Severo and A. Girardi, "Projeto automatico de blocos analogicos integrados usando metodos de otimizacao nao-linear," XV Workshop Iberchip, vol. 1, March 2009.
9. J. Kennedy and R. C. Eberhart, "Particle swarm optimization," in IEEE International Conference on Neural Networks, pp. 1942--1948, IEEE Service Center, 1995.
10. M. Fakhfakh, Y. Cooren, A. Sallem, M. Loulou, and P. Siarry, "Analog circuit design optimization through the particle swarm optimization technique," Analog Integrated Cir Process, vol. 63, pp. 71--82, 2010.

Index Terms

• Hardware

  • Electronic design automation

    • Physical design (EDA)