Pierre-Emmanuel Gaillardon
ABSTRACT
Thanks to recent technology advances, the exploration of the vertical dimension has been shown to be more than a dream for designers. Among those technologies, the vertical transistor has not been exploited yet. This paper describes a novel implementation of logic gates fully benefiting of nanowire-based vertical transistors embedded within the metal lines. The logic design in this technology is explored and its performance is evaluated. A comparison made on an equivalent technology node shows that our cells reduce area and delay by a factor of 31x and 2x respectively. Large reconfigurable logic circuits have been benchmarked showing an improvement of area and delay by 46% and 48% on average.
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Cross Ref
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- V. Renard et al., Catalyst preparation for CMOS-compatible silicon nanowire synthesis, Nature Nanotechnology, 2009.Google ScholarCross Ref
- J. Goldberger et al., Silicon Vertically Integrated Nanowire Field Effect Transistors, Nano Letters, Vol. 6, No 5, 2006.Google ScholarCross Ref
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Index Terms
- Can we go towards true 3-D architectures?
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