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Enabling system-level modeling of variation-induced faults in networks-on-chips

Published: 05 June 2011 Publication History

Abstract

Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However, these evaluations assume random fault distributions, which result in 52%--81% inaccuracy. We propose an accurate circuit-level fault-modeling tool, which can be plugged into any system-level NoC simulator, quantify the system-level impact of PV-induced faults at runtime, pinpoint fault-prone router components that should be protected, and accurately evaluate alternative resilient multi-core designs.

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Cited By

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  • (2022)HREN: A Hybrid Reliable and Energy-Efficient Network-on-Chip ArchitectureIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2022.3147407(1-1)Online publication date: 2022
  • (2020)FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9181268(1-5)Online publication date: Oct-2020
  • (2019)High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8714869(1166-1171)Online publication date: Mar-2019
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    cover image ACM Conferences
    DAC '11: Proceedings of the 48th Design Automation Conference
    June 2011
    1055 pages
    ISBN:9781450306362
    DOI:10.1145/2024724
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 05 June 2011

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    Author Tags

    1. fault modeling
    2. networks-on-chips
    3. variation

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    Cited By

    View all
    • (2022)HREN: A Hybrid Reliable and Energy-Efficient Network-on-Chip ArchitectureIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2022.3147407(1-1)Online publication date: 2022
    • (2020)FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9181268(1-5)Online publication date: Oct-2020
    • (2019)High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8714869(1166-1171)Online publication date: Mar-2019
    • (2018)Runtime Techniques to Mitigate Soft Errors in Network-on-Chip (NoC) ArchitecturesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.266406637:3(682-695)Online publication date: Mar-2018
    • (2018)RETUNES: Reliable and Energy-Efficient Network-on-Chip Architecture2018 IEEE 36th International Conference on Computer Design (ICCD)10.1109/ICCD.2018.00079(488-495)Online publication date: Oct-2018
    • (2018)Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2018.00048(480-491)Online publication date: Feb-2018
    • (2017)On-Chip Networks, Second EditionSynthesis Lectures on Computer Architecture10.2200/S00772ED1V01Y201704CAC04012:3(1-210)Online publication date: 17-Jun-2017
    • (2017)A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical ModelIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.273600425:11(3099-3112)Online publication date: Nov-2017
    • (2017)System-level simulator for process variation influenced synchronous and asynchronous NoCs2017 30th IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC.2017.8226065(298-303)Online publication date: Sep-2017
    • (2017)Architecture level analysis for process variation in synchronous and asynchronous Networks-on-ChipJournal of Parallel and Distributed Computing10.1016/j.jpdc.2016.12.019102:C(175-185)Online publication date: 1-Apr-2017
    • Show More Cited By

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