Christian Fabre
ABSTRACT
PRO3D tackles two 3D technologies and their consequences on stacked architectures and software stack: through silicon vias (TSV) and liquid cooling. 3D memory hierarchies and the thermal impact of software on the 3D stack are mainly explored. The PRO3D software development flow is based on a rigorous assembly of software components and monitors the thermal integrity of the 3D stack. PRO3D experiments are mainly targeted on P2012, an industrial embedded manycore platform.
- A. Basu, S. Bensalem, M. Bozga, J. Combaz, M. Jaber, T.-H. Nguyen, and J. Sifakis. Rigorous component-based design using the BIP framework. IEEE Software, Special Edition -- Software Components: Beyond Programming, June 2011. Google Scholar
Digital Library
- L. Benini, D. Bertozzi, A. Bogliolo, F. Menichelli, and M. Olivieri. MPARM: Exploring the Multi-Processor SoC Design Space with SystemC. J. VLSI Signal Process, 41(2):169--182, 2005. Google ScholarDigital Library
- D. Bortolotti, F. Paterna, C. Pinto, A. Marongiu, M. Ruggiero, and L. Benini. Exploring instruction caching strategies for tightly-coupled shared-memory clusters. In In Int. Symp. on Systems-on-Chip, 2011.Google ScholarCross Ref
- P. Bourgos, A. Basu, M. Bozga, S. Bensalem, J. Sifakis, and K. Huang. Rigorous system level modeling and analysis of mixed HW/SW systems. In Proceedings of MEMOCODE, pages 11--20. IEEE/ACM, 2011.Google ScholarDigital Library
- W. Haid, M. Keller, K. Huang, I. Bacivarov, and L. Thiele. Generation and calibration of compositional performance analysis models for multi-processor systems. In Proc. Intl Conference on Systems, Architectures, Modeling and Simulation, pages 92--99, Samos, Greece, 2009. IEEE. Google ScholarDigital Library
- K. Huang, W. Haid, I. Bacivarov, M. Keller, and L. Thiele. Embedding Formal Performance Analysis into the Design Cycle of MPSoCs for Real-time Streaming Applications. 2011.Google Scholar
- A. Marongiu, P. Burgio, and L. Benini. Vertical stealing: robust, locality-aware do-all workload distribution for 3D MPSoCs. In V. Kathail, R. Tatge, and R. Barua, editors, CASES, pages 207--216. ACM, 2010. Google ScholarDigital Library
- P. Marwedel, J. Teich, G. Kouveli, I. Bacivarov, L. Thiele, S. Ha, C. Lee, Q. Xu, and L. Huang. Mapping of Applications to MPSoCs. CODES+ISSS'11, 2011. Taiwan. Google ScholarDigital Library
- PRO3D -- Programming for Future 3D Multicore Architectures, 2010. http://pro3d.eu.Google Scholar
- D. Rai, H. Yang, I. Bacivarov, J.-J. Chen, and L. Thiele. Worst-case temperature analysis for real-time systems. DATE11, Grenoble, France, 2011.Google ScholarCross Ref
- M. Ruggiero, F. Angiolini, F. Poletti, D. Bertozzi, L. Benini, and R. Zafalon. Scalability analysis of evolving SoC interconnect protocols. In Int. Symp. on Systems-on-Chip, pages 169--172, 2004.Google Scholar
- M. M. Sabry, M. Ruggiero, and P. G. Del Valle. Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs. In Proceedings of the 20th symposium on Great lakes symposium on VLSI, GLSVLSI '10, pages 305--310, New York, NY, USA, 2010. ACM. Google ScholarDigital Library
- L. Schor, H. Yang, I. Bacivarov, and L. Thiele. Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study. In Proc. International Workshop on Power and Timing Modeling, Optimization, and Simulation (PATMOS), volume 6951 of LNCS, pages 288--297. Springer, 2011. Google ScholarDigital Library
- A. Sridhar, A. Vincenzi, M. Ruggiero, T. Brunschwiler, and D. Atienza. Compact transient thermal model for 3D ICs with liquid cooling via enhanced heat transfer cavity geometries. In Thermal Investigations of ICs and Systems (THERMINIC), 2010 16th International Workshop on, pages 1--6, 2010.Google Scholar
- STM and CEA. Platform 2012: A Manycore Programmable Accelerator for Ultra-Efficient Embedded Computing in Nanometer Technology, Nov. 2010. Whitepaper.Google Scholar
- L. Thiele, I. Bacivarov, W. Haid, and K. Huang. Mapping Applications to Tiled Multiprocessor Embedded Systems. In Proc. Int'l Conf. on Application of Concurrency to System Design (ACSD), pages 29--40, 2007. Google ScholarDigital Library
- A. Vincenzi, A. Sridhar, M. Ruggiero, and D. Atienza. Fast thermal simulation of 2D/3D integrated circuits exploiting neural networks and GPUs. In Proceedings of the 17th IEEE/ACM international symposium on low-power electronics and design, ISLPED '11, pages 151--156, Piscataway, NJ, USA, 2011. IEEE Press. Google ScholarDigital Library
Index Terms
- PRO3D: programming for future 3D manycore architectures
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