research-article

Heterogeneous integration to simplify many-core architecture simulations

Authors:

M. Irfan Uddin,

Jaroslav Sýkora,

Leoš KafkaAuthors Info & Claims

RAPIDO '12: Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

Pages 17 - 24

https://doi.org/10.1145/2162131.2162134

Published: 23 January 2012 Publication History

Abstract

The EU Apple-CORE project has explored the design and implementation of novel general-purpose many-core chips featuring hardware microthreading and hardware support for concurrency management. The introduction of the latter in the cores ISA has required simultaneous investigation into compilers and multiple layers of the software stack, including operating systems. The main challenge in such vertical approaches is the cost of implementing simultaneously a detailed simulation of new hardware components and a complete system platform suitable to run large software bench-maks. In this paper, we describe our use case and our solutions to this challenge.

References

[1]

A. Baumann, P. Barham, P.-E. Dagand, T. Harris, R. Isaacs, S. Peter, T. Roscoe, A. Schüpbach, and A. Singhania. The multikernel: a new os architecture for scalable multicore systems. In Proc. ACM SIGOPS 22nd symposium on Operating systems principles, SOSP'09, pages 29--44, New York, NY, USA, 2009. ACM.

Digital Library

[2]

I. Bell, N. Hasasneh, and C. Jesshope. Supporting microthread scheduling and synchronisation in CMPs. International Journal of Parallel Programming, 34:343--381, 2006.

Digital Library

[3]

N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt. The M5 simulator: Modeling networked systems. IEEE Micro, 26:52--60, 2006.

Digital Library

[4]

K. Bousias, L. Guang, C. Jesshope, and M. Lankamp. Implementation and evaluation of a microthread architecture. Journal of Systems Architecture, 55(3):149--161, 2008.

Digital Library

[5]

K. Bousias, N. Hasasneh, and C. Jesshope. Instruction level parallelism through microthreading -- a scalable approach to chip multiprocessors. The Computer Journal, 49(2):211--233, March 2006.

Digital Library

[6]

D. Chiou, D. Sunwoo, J. Kim, N. A. Patil, W. Reinhart, D. E. Johnson, J. Keefe, and H. Angepat. FPGA-accelerated simulation technologies (FAST): Fast, full-system, cycle-accurate simulators. In Proc 40th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 40, pages 249--261, Washington, DC, USA, 2007. IEEE Computer Society.

Digital Library

[7]

M. Danek, L. Kafka, L. Kohout, and J. Sykora. Instruction set extensions for multi-threading in LEON3. In Z. K. et al., editor, Proc. 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'2010), pages 237--242. IEEE, 2010.

[8]

D. Flynn. AMBA: enabling reusable on-chip designs. IEEE Micro, 17(4):20--27, jul/aug 1997.

Digital Library

[9]

J. Gaisler. A portable and fault-tolerant microprocessor based on the SPARC v8 architecture. In Proc. International Conference on Dependable Systems and Networks (DSN'02), pages 409--415. IEEE, 2002.

Digital Library

[10]

J. Gaisler, E. Catovic, and S. Habinc. GRLIB IP Library User's Manual. Gaisler Research, 2007.

[11]

C. Grelck and S.-B. Scholz. SAC: a functional array language for efficient multi-threaded execution. International Journal of Parallel Programming, 34(4):383--427, Aug 2006.

Digital Library

[12]

M. A. Hicks, M. W. van Tol, and C. R. Jesshope. Towards Scalable I/O on a Many-core Architecture. In International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), pages 341--348. IEEE, July 2010.

[13]

HyperTransport Consortium. The future of high-performance computing: Direct low-latency peripheral-to-CPU connection, September 2005.

[14]

Intel Corporation. Intel® Core#8482; i7-900 desktop processor extreme edition series and Intel® Core#8482; i7-900 desktop processor series Datasheet, Volume 1, document # 320834-00, February 2010.

[15]

P. Konecny. Introducing the Cray XMT. In Proc. Cray User Group meeting (CUG'07), 411 First Avenue South, Seattle, WA 9810, USA, May 2007. Cray Inc.

[16]

D. McCullough. uClinux for Linux programmers. Linux Journal, (123):34--36, 38, July 2004.

Digital Library

[17]

E. B. Nightingale, O. Hodson, R. McIlroy, C. Hawblitzel, and G. Hunt. Helios: heterogeneous multiprocessing with satellite kernels. In Proc. ACM SIGOPS 22nd symposium on Operating systems principles, SOSP '09, pages 221--234, New York, NY, USA, 2009. ACM.

Digital Library

[18]

A. Schüpbach, S. Peter, A. Baumann, T. Roscoe, P. Barham, T. Harris, and R. Isaacs. Embracing diversity in the barrelfish manycore operating system. In Proceedings of the Workshop on Managed Many-Core Systems. ACM, June 2008.

[19]

J. Sykora, L. Kafka, M. Danek, and L. Kohout. Analysis of execution efficiency in the microthreaded processor UTLEON3. volume 6566 of Lecture Notes in Computer Science, pages 110--121. Springer, 2011.

Digital Library

[20]

M. I. Uddin, M. W. van Tol, and C. R. Jesshope. High level simulation of SVP many-core systems. Parallel Processing Letters, 21(4):413--438, December 2011.

[21]

T. von Eicken, D. E. Culler, S. C. Goldstein, and K. E. Schauser. Active messages: a mechanism for integrated communication and computation. In ISCA '92: Proc. 19th annual International Symposium on Computer Architecture, pages 256--266, New York, NY, USA, 1992. ACM.

Digital Library

[22]

J. Wawrzynek, D. Patterson, M. Oskin, S.-L. Lu, C. Kozyrakis, J. Hoe, D. Chiou, and K. Asanovic. RAMP: Research accelerator for multiple processors. IEEE Micro, 27(2):46--57, March-April 2007.

Digital Library

[23]

D. Wentzlaff and A. Agarwal. Factored operating systems (fos): the case for a scalable operating system for multicores. SIGOPS Oper. Syst. Rev., 43:76--85, April 2009.

Digital Library

[24]

D. Wentzlaff, C. Gruenwald, N. Beckmann, K. Modzelewski, A. Belay, L. Youseff, J. Miller, and A. Agarwal. A unified operating system for clouds and manycore: fos. Technical Report MIT-CSAIL-TR-2009-059, Computer Science and Artificial Intelligence Lab, MIT, November 2009.

[25]

S. Wilton and N. Jouppi. Cacti: an enhanced cache access and cycle time model. Solid-State Circuits, IEEE Journal of, 31(5):677--688, may 1996.

[26]

L. Zhang and C. R. Jesshope. On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores. In Bouge and et al., editors, Euro-Par Workshops, volume 4854 of LNCS, pages 38--48. Springer, 2007.

Digital Library

Cited By

Uddin I(2017)One-IPC high-level simulation of microthreaded many-core architecturesInternational Journal of High Performance Computing Applications10.1177/109434201558449531:2(152-162)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1177/1094342015584495
Uddin I(2015)High-level simulation of concurrency operations in microthreaded many-core architecturesGSTF Journal on Computing (JoC)10.7603/s40601-014-0021-94:3Online publication date: 13-Dec-2015
https://doi.org/10.7603/s40601-014-0021-9
Chen KChen C(2014)An OpenCL runtime system for a heterogeneous many-core virtual platform2014 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2014.6865605(2197-2200)Online publication date: Jun-2014
https://doi.org/10.1109/ISCAS.2014.6865605
Show More Cited By

Index Terms

Heterogeneous integration to simplify many-core architecture simulations

Recommendations

Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms

In this contribution we present a new paradigm and methodology for the Network-on-chip (NoC) based design of complex hardware/software systems. While classical industrial design platforms represent dedicated fixed architectures for specific applications,...
Embedded architecture description language

In the state-of-the-art hardware/software (HW/SW) co-design of embedded systems, there is a lack of sufficient support for architectural specifications across HW/SW boundaries. Such an architectural specification ought to capture both hardware and ...
Profiling soft-core processor applications for hardware/software partitioning

In this paper, we present an efficient approach to HW/SW partitioning of applications targeted for embedded softcore SoPC and programmable logic. The methodology is based on the iterative performance analysis of the initial functional SW description and ...

Comments

Information & Contributors

Information

Published In

cover image ACM Other conferences

RAPIDO '12: Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

January 2012

44 pages

ISBN:9781450311144

DOI:10.1145/2162131

Conference Chairs:
Daniel Gracia Pérez
CEA LIST, France
,
Smail Niar
University of Valenciennes/INRIA, France
,
Cristina Silvano
Politecnico di Milano, Italy
,
Morteza Biglari Abhari
The University of Auckland, New Zealand

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

HiPEAC: HiPEAC Network of Excellence

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 January 2012

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

Seventh Framework Programme

Conference

RAPIDO '12

Sponsor:

HiPEAC

RAPIDO '12: Methods and Tools

January 23, 2012

Paris, France

Acceptance Rates

Overall Acceptance Rate 14 of 28 submissions, 50%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

6
Total Citations
View Citations
198
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 05 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Uddin I(2017)One-IPC high-level simulation of microthreaded many-core architecturesInternational Journal of High Performance Computing Applications10.1177/109434201558449531:2(152-162)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1177/1094342015584495
Uddin I(2015)High-level simulation of concurrency operations in microthreaded many-core architecturesGSTF Journal on Computing (JoC)10.7603/s40601-014-0021-94:3Online publication date: 13-Dec-2015
https://doi.org/10.7603/s40601-014-0021-9
Chen KChen C(2014)An OpenCL runtime system for a heterogeneous many-core virtual platform2014 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2014.6865605(2197-2200)Online publication date: Jun-2014
https://doi.org/10.1109/ISCAS.2014.6865605
Uddin IPoss RJesshope C(2014)Cache-based high-level simulation of microthreaded many-core architecturesJournal of Systems Architecture10.1016/j.sysarc.2014.05.00360:7(529-552)Online publication date: Aug-2014
https://doi.org/10.1016/j.sysarc.2014.05.003
Poss RLankamp MYang QFu JUddin IJesshope C(2013)MGSim — A simulation environment for multi-core research and education2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)10.1109/SAMOS.2013.6621109(80-87)Online publication date: Jul-2013
https://doi.org/10.1109/SAMOS.2013.6621109
Poss RLankamp MYang QFu Jvan Tol MJesshope C(2012)Apple-COREProceedings of the 2012 15th Euromicro Conference on Digital System Design10.1109/DSD.2012.25(501-508)Online publication date: 5-Sep-2012
https://dl.acm.org/doi/10.1109/DSD.2012.25

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten