Parallel pipelined FFT architectures with reduced number of delays

ABSTRACT

This paper presents a novel approach to design four and eight parallel pipelined fast Fourier transform (FFT) architectures using folding transformation. The approach is based on use of decimation in time algorithms which reduce the number of delay elements by 33% compared to the decimation in frequency based designs. The number of delay elements required for an N-point FFT architecture is N - 4 which is comparable to that of delay feedback schemes. The number of complex adders required is only 50% of those in the delay feedback designs. The proposed approach can be extended to any radix-2ⁿ based FFT algorithms. The proposed architectures are feed-forward designs and can be pipelined by more stages to increase the throughput. Further, a novel four parallel 128-point FFT architecture is derived using the proposed approach. It is shown that a radix-2⁴ 4-parallel 128-point design requires 124 delay elements, 28 complex adders, and four full complex multipliers.

References

1. N. Weste, D. J. Skellern, "VLSI for OFDM," IEEE Communications Magazine, vol.36, no.10, pp.127--131, Oct 1998.
2. A. Wang, A. Chandrakasan, "Energy-efficient DSPs for wireless sensor networks," IEEE Signal Processing Magazine, vol.19, no.4, pp.68--78, Jul 2002.
3. Y. Park, et al., "Seizure Prediction with Spectral Power of EEG using Cost-Sensitive Support Vector Machines," Epilepsia, vol. 52, pp. 1761--1770, Oct. 2011.
4. S. He and M. Torkelson, "A new approach to pipeline FFT processor," Proc. of IPPS, 1996, pp. 766 -- 770.
5. J. Lee, H. Lee, S. I. Cho and S. S. Choi, "A High-Speed two parallel radix-2⁴ FFT/IFFT processor for MB-OFDM UWB systems," IEEE Inter. Symp. on Circuits and Systems, pp. 4719--4722, May 2006.
6. Y. W. Lin, et al., "A 1-GS/s FFT/IFFT processor for UWB applications," IEEE Journal of Solid-state Circuits, vol. 40, no.8 pp. 1726--1735, Aug. 2005.
7. M. Shin and H. Lee, "A high-speed four parallel radix-2⁴ FFT/IFFT processor for UWB applications", IEEE ISCAS 2008, pp. 960 -- 963, May 2008.
8. M. Ayinala, M. Brown, K. K. Parhi, "Pipelined parallel FFT architectures via folding transformation," IEEE Transactions on VLSI Systems, vol. 20, 2012.
9. Z. Wang et al., "A Novel FFT Processor for OFDM UWB Systems," Proc. IEEE APCCAS, pp. 374--377, Dec. 2006.
10. S. Qiao et al., "An Area and Power Efficient FFT Processor for UWB Systems," Proc. IEEE WICOM, Sept. 2007, pp. 582--585.
11. S.-N Tang, J. Tsai, T.-Y. Chang, "A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications," IEEE Transactions on Circuits and Systems II: Express Briefs, vol.57, no.6, pp.451--455, June 2010.
12. K .K. Parhi, et al., "Synthesis of control circuits in folded pipelined DSP architectures," IEEE Journal of Solid State Circuits, vol. 27, no. 1, pp. 29--43, 1992.
13. K. K. Parhi, "Systematic synthesis of DSP data format converters using lifetime analysis and forward-backward register allocation," IEEE TCAS - II, vol. 39, no. 7, pp. 423--440, July 1992..

Index Terms

• Hardware

  • Electronic design automation

    • High-level and register-transfer level synthesis

  • Very large scale integration design

    • VLSI packaging

      • Input / output styles