ABSTRACT
Simulation-based verification is an integral part of a modern microprocessor's design effort. Commonly, several checking techniques are deployed alongside the simulator to detect and localize each functional bug manifestation. Among these, a widespread technique entails comparing a microprocessor design's outputs with a golden model at the architectural granularity, instruction-by-instruction. However, due to exponential growth in design complexity, the performance of software-based simulation falls far short of achieving an acceptable level of coverage, which typically requires billions of simulation cycles. Hence, verification engineers rely on simulation acceleration platforms. Unfortunately, the intrinsic characteristics of these platforms make the adoption of the checking solutions mentioned above a challenging goal: for instance, the lockstep execution of a software checker together with the design's simulation is no longer feasible.
To address this challenge we propose an innovative solution for instruction-by-instruction (IBI) checking tailored to acceleration platforms. We provide novel design techniques to decouple event tracing from checking by including specialized tracing logic and by adding a post-simulation checking phase. Note that simulation performance in acceleration platforms degrades when increasing the number of signals that are traced; hence, it is imperative to generate a compact summary of the information required for checking, collecting and tracing only a few bits of information per cycle.
- A. Adir, E. Almog, L. Fournier, E. Marcus, M. Rimon, M. Vinov, and A. Ziv. Genesys-Pro: Innovations in test program generation for functional processor verification. IEEE Design & Test, 21(2), 2004. Google ScholarDigital Library
- T. M. Austin. DIVA: A reliable substrate for deep submicron microarchitecture design. In Proc. MICRO, 1999. Google ScholarDigital Library
- M. Boulé, J.-S. Chenard, and Z. Zilic. Adding debug enhancements to assertion checkers for hardware emulation and silicon debug. In Proc. ICCD, 2006.Google ScholarCross Ref
- O. Caty, P. Dahlgren, and I. Bayraktaroglu. Microprocessor silicon debug based on failure propagation tracing. In IEEE Transactions on Computers, 2005.Google Scholar
- Y.-S. Chang, S. Lee, I.-C. Park, and C.-M. Kyung. Verification of a microprocessor using real world applications. In Proc. DAC, 1999. Google ScholarDigital Library
- J. Darringer, E. Davidson, D. Hathaway, B. Koenemann, M. Lavin, J. Morrell, K. Rahmat, W. Roesner, E. Schanzenbach, G. Tellez, and L. Trevillyan. EDA in IBM: past, present, and future. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(12), 2000. Google ScholarDigital Library
- L. Fournier, Y. Arbetman, and M. Levinger. Functional verification methodology for microprocessors using the Genesys test-program generator. In Proc. DATE, pages 434--441, March 1999. Google ScholarDigital Library
- G. Ganapathy, R. Narayan, C. Jorden, M. Wang, and J. Nishimura. Hardware emulation for functional verification of K5. In Proc. DAC, 1996. Google ScholarDigital Library
- J. M. Ludden et al. Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems. IBM Journal of Research and Development, 46(1):53--76, 2002. Google ScholarDigital Library
- A. Mayer, H. Siebert, and K. McDonald-Maier. Boosting debugging support for complex systems on chip. Computer, 40(4), 2007. Google ScholarDigital Library
- S.-B. Park, T. Hong, and S. Mitra. Post-silicon bug localization in processors using instruction footprint recording and analysis (IFRA). IEEE Trans. on CAD, 28(10), 2009. Google ScholarDigital Library
- V. Popescu and B. McNamara. Innovative verification strategy reduces design cycle time for high-end SPARC processor. In Proc. DAC, 1996. Google ScholarDigital Library
- D. W. Victor et al. Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems. IBM Journal of Research and Development, 49(4), 2005. Google ScholarDigital Library
- J.-S. Yim, Y.-H. Hwang, C.-J. Park, H. Choi, W.-S. Yang, H.-S. Oh, I.-C. Park, and C.-M. Kyung. A C-based RTL design verification methodology for complex microprocessor. In Proc. DAC, 1997. Google ScholarDigital Library
Index Terms
- Checking architectural outputs instruction-by-instruction on acceleration platforms
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