Jonathan Bachrach
ABSTRACT
In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. By embedding Chisel in the Scala programming language, we raise the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to map to either FPGAs or to a standard ASIC flow for synthesis. This paper presents Chisel, its embedding in Scala, hardware examples, and results for C++ simulation, Verilog emulation and ASIC synthesis.
- Bellows, P., and Hutchings, B. JHDL--an HDL for reconfigurable systems. IEEE Symposium on FPGAs for Custom Computing Machines (1998). Google Scholar
Digital Library
- Berry, G., and Gonthier, G. The Esterel synchronous programming language: Design, semantics, implementation. Science of Computer Programming 10, 2 (1992). Google ScholarDigital Library
- Bluespec Inc. Bluespec(tm) SystemVerilog Reference Guide: Description of the Bluespec SystemVerilog Language and Libraries. Waltham, MA, 2004.Google Scholar
- Goldstein, S., and Budiu, M. Fast compilation for pipelined reconfigurable fabrics. ACM/FPGA Symposium on Field Programmable Gate Arrays (1999). Google ScholarDigital Library
- Hauser, J. The softfloat and testfloat packages. http://www.jhauser.us/arithmetic/index.html.Google Scholar
- Jenning, J., and Beuscher, E. Verischemelog: Verilog embedded in scheme. Proceedings of DSL'99: The 2nd conference on Domain Specific Languages (Oct 1999). Google ScholarDigital Library
- Li, Y., and Leeser, M. HML--a novel hardware description language and its translation to VHDL. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8, 1 (Oct 2000). Google ScholarDigital Library
- Odersky, M. e. a. Scala programming language. http://www.scala-lang.org/.Google Scholar
- Shacham, O., Azizi, O., Wachs, M., Qadeer, W., Asgar, Z., Kelley, K., Stevenson, J., Solomatnikov, A., Firoozshahian, A., Lee, B., Richardson, S., and M., H. Rethinking digital design: Why design must change. IEEE Micro (Nov/Dec 2010). Google ScholarDigital Library
Index Terms
- Chisel: constructing hardware in a Scala embedded language
Recommendations
Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only)
FPGA '10: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arraysAn Application Specific Inflexible FPGA (ASIF) is an FPGA with reduced flexibility that can implement a set of application circuits which will operate at different times. Application circuits are initially placed and routed on an FPGA in such a way that ...
Application-Specific FPGA using heterogeneous logic blocks
This work presents a new automatic mechanism to explore the solution space between Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). This new solution is termed as an Application-Specific Inflexible FPGA (ASIF) ...
Designing Run-Time Reconfigurable Systems with JHDL
Run-time reconfigurable (RTR) systems are FPGA-based systems that reconfigure FPGAs during execution to alter hardware organization and composition to meet the varying needs of applications as they execute. These systems are difficult to describe with ...
Comments