Evaluation of multithreaded uniprocessors for commercial application environments

ABSTRACT

As memory speeds grow at a considerably slower rate than processor speeds, memory accesses are starting to dominate the execution time of processors, and this will likely continue into the future. This trend will be exacerbated by growing miss rates due to commercial applications, object-oriented programming and micro-kernel based operating systems. We examine the use of coarse-grained multithreading to address this important problem in uniprocessor on-line transaction processing environments where there is a natural, coarse-grained parallelism between the tasks resulting from transactions being executed concurrently, with no application software modifications required. Our results suggest that multithreading can provide significant performance improvements for uniprocessor commercial computing environments.

References

1. 1.A. Agarwal, J. Kubiatowicz, D. Kranz, B. Lim, D. Yeung, G. D'Souza, and M. Parkin. Sparcle: An evolutionary design for large-scale multiprocessors. IEEE Micro, 13(3):48-60, 1993.
2. 2.R. Alverson, D. Callahan, D. Cummings, B. Koblenz, A. Porterfield and B. Smith. The Tern computer system. In Proc. Intl. Conf. Supercomputing, pp. 1-6, June 1990.
3. 3.T. Anderson, H. Levy, B. Bershad and E. Lazowska. The interaction of architecture and operating system design. In Proc. intl. Conf. Arch. Support for Prog. Lang. and Op. Sys., pp. 108-120, April 1991.
4. 4.K. Boland and A. Dollas. Predicting and precluding problems with memory latency. IEEE Micro, 14(4):59- 67, 1994.
5. 5.B. Calder, D. Grunwald and B. Zorn. Quantifying behavioral differences between C and C++ programs. Tech. Rep. CU-CS-698-94, University of Colorado, Jan. 1994.
6. 6.Z. Cvetanovic and C. Bhandarkar. Performance characterization of the Alpha 21164 microprocessor using TP and SPEC workloads. In Prec. High-Perf. Comp. Arch., pp. 270-280, Feb. 1996.
7. 7.R. J. Eickemeyer, R. E. Johnson, S. R. Kunkel and J. A. Rose. An analysis of multithreading in PowerPCTM processors. Conf. Tech. Rep. 07.2190, IBM AS/400 Division, Sept. 1994.
8. 8.R. J. Eickemeyer, R. E. Johnson, S. R. Kunkel, S. Liu and M. S. Squillante. Performance analysis of multithreaded uniprocessors under commercial workloads. Conf. Tech. Rep., IBM Research Division, Dec. 1994.
9. 9.R. J. Eickemeyer, R. E. Johnson, S. R. Kunkel, M. S. Squillante and S. Liu. Evaluation of multithreaded uniprocessors for commercial application environments. Tech. Rep., IBM Research Division, Nov. 1995.
10. 10.A. Gupta, J. Hennessy, K. Gharachorloo, T. Mowry and W.-D. Weber. Comparative evaluation of latency reducing and tolerating techniques, in Proc. Intl. Syrup. Comp. Arch., pp. 254-263, May 1991.
11. 11.N. P. Jouppi and S. J.E. Wilton. Tradeoffs in two-level on-chip caching. In Proc. Intl. Syrnp. Cornp. Arch., pp. 34-45, April 1994.
12. 12.K. Kurihara, D. Chaiken and A. Agarwal. Latency tolerance through multithreading in large scale multiprocessors. In Proc. Intl. Syrnp. Shared Memory Multiprocessing, pp. 91-101, April 1991.
13. 13.J. Laudon, A. Gupta and M. Horowitz. Interleaving: A multithreading technique targeting multiprocessors and workstations. In Proc. Intl. Conf. Arch. Support for Prog. Lang. and Op. Sys., pp. 308-318, Oct. 1994.
14. 14.D. Lenosld, J. Laudon, K. Gharachorloo, A. Gupta and J. Hennessy. The directory-based cache coherence protocol for the DASH multiprocessor. In Proc. Intl. Syrup. Cornp. Arch., pp. 148-159, May 1990.
15. 15.A. Maynard, C. Donnelly and B. Olzewski. Contrasting characteristics and cache performance of technical and multi-user commercial workloads. In Proc. Intl. Conf. Arch. Support.for Prog. Lang. and Op. Sys., Oct. 1994.
16. 16.M. S. Squillante. Analytic modehng of processor utilization in multithreaded processor architectures. Tech. Rep. RC 19543, IBM Research Division, April 1994.
17. 17.D. Tullsen and S. J. Eggers. Limitations of cache prefetching on a bus-based multiprocessor, in Proc. Intl. Syrup. Comp. Arch., pp. 278-288, June 1995.
18. 18.D. Tullsen, S. J. Eggers and H. Levy. Simultaneous multithreading: Maximizing on-chip parallelism. In Proc. Intl. Syrup. Comp. Arch., pp. 392-403, June 1995.
19. 19.W.-D. Weber and A. Gupta. Exploring the benefits of multiple hardware contexts in a multiprocessor architecture: Preliminary results. In Proc. Intl. Syrup. Comp. Arch., pp. 273-280, June 1989.
20. 20.W. Wulf and S. McKee. Hitting the memory wall: Implications of the obvious. Comp. Arch. News, 23(1)20- 24, 1995.

Index Terms

• Computer systems organization

• Computing methodologies

  • Modeling and simulation

• Hardware

  • Integrated circuits

    • Semiconductor memory

• Software and its engineering

  • Software organization and properties

    • Contextual software domains

      • Operating systems

        • Process management

          • Multiprocessing / multiprogramming / multitasking