A novel AES-256 implementation on FPGA using co-processor based architecture

ABSTRACT

Efficient hardware architecture for cryptographic algorithms are of utmost need for implementing secured data communication in embedded applications. The hardware implementation of the algorithms though provides less flexibility, but are faster and requires less resource as compared to the software implementation, and hence ideally suited for target specific embedded systems. Though, there exist quite a few research works that propose hardware design for implementing cryptographic algorithm on various hardware platforms like application specific integrated circuit (ASIC), field programmable gate array (FPGA) and micro-controllers, still there lies the need of better hardware design in terms of larger key values, higher throughput and less resource utilization.

References

1. Embedded radio modules (802.11 b/g). datasheet. http://www.quatech.com, 2006.
2. I. Algredo-Badillo, C. Feregrino-Uribe, R. Cumplido, and M. Morales-Sandoval. Efficient hardware architecture for the aes-ccm protocol of the ieee 802.11i standard. Comput. Electr. Eng., 36(3):565--577, May 2010.
3. Altera. Introduction to the altera nios ii soft processor. ftp://ftp.altera.com/up/pub/Tutorials/DE2/Computer_Organization/tut_nios2_ introduction.pdf.
4. D. Bae, G. Kim, J. Kim, S. Park, and O. Song. An efficient design of ccmp for robust security network. In Information Security and Cryptology - ICISC 2005, 2005.
5. E. Canto, F. Fons, and M. Lopez. Reconfigurable opb coprocessors for a microblaze self-reconfigurable soc mapped on spartan-3 fpgas. In IEEE Industrial Electronics, IECON 2006 - 32nd Annual Conference on, pages 4940--4944, nov. 2006.
6. R. Corporation. Mpc8641d powerpc advanced mezzanine card. datasheet, 2006.
7. J. Daemen and V. Rijmen. Advanced encryption standard (aes). NIST, U. S.department of Commerce, November 2001, 1(1):1--51, November 2001.
8. S. Fernando and H. Yajun. In Field-Programmable Custom Computing Machines, 2005. FCCM 2005. 13th Annual IEEE Symposium on.
9. W. Ford and B. S. Kaliski, Jr. Server-assisted generation of a strong secret from a password. In Proceedings of the 9th IEEE International Workshops on Enabling Technologies: Infrastructure for Collaborative Enterprises, WETICE '00, pages 176--180, Washington, DC, USA, 2000. IEEE Computer Society.
10. J. A. Garay, R. Gennaro, C. Jutla, and T. Rabin. Secure distributed storage and retrieval. Theoretical Computer Science, 243(1âĂŞ2):363--389, 2000.
11. P. Gutmann. An open-source cryptographic coprocessor. In Proceedings of the 9th conference on USENIX Security Symposium - Volume 9, SSYM'00, pages 8--8, Berkeley, CA, USA, 2000. USENIX Association.
12. J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 3 edition, 2003.
13. I. Hi/fn. The wimax security processor. datasheet. http://www.hifn.com.
14. X. Inc. Platform studio and the embedded development kit (edk). http://www.xilinx.com/tools/platform.htm.
15. H. Y. Jang, J. H. Shim, J. H. Suk, I. C. Hwang, and J. R. Choi. Compatible design of ccmp and ocb aes cipher using separated encryptor and decryptor for ieee 802.11i. In Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on, volume 3, pages III -- 645--8 Vol.3, may 2004.
16. H. Li and J. Li. A high performance sub-pipelined architecture for aes. In Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, pages 491--496, oct. 2005.
17. P. MacKenzie and M. Reiter. Networked cryptographic devices resilient to capture. In Security and Privacy, 2001. S P 2001. Proceedings. 2001 IEEE Symposium on, pages 12--25, 2001.
18. O.-c. Mourad, S.-M. Lotfy, M. Noureddine, B. Ahmed, and T. Camel. Aes embedded hardware implementation. In Adaptive Hardware and Systems, 2007. AHS 2007. Second NASA/ESA Conference on, pages 103--109, aug. 2007.
19. S. J. Park. Analysis of aes hardware implementations. http://www.citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.122...pdf.
20. A. Samiah, A. Aziz, and N. Ikram. A secure framework for robust secure wireless network (rsn) using aes-ccmp. In fourth international Bhurban conference on applied sciences and technology, June 2005.
21. S. Sau, C. Pal, and A. Chakrabarti. Design and implementation of real time secured rs232 link for multiple fpga communication. In Proceedings of the 2011 International Conference on Communication, Computing & Security, ICCCS '11, pages 391--396, New York, NY, USA, 2011. ACM.
22. N. Smyth, M. McLoone, and J. McCanny. Wlan security processor. Circuits and Systems I: Regular Papers, IEEE Transactions on, 53(7):1506--1520, july 2006.
23. W. Stallings. Cryptography and network security - principles and practice (3. ed.). Prentice Hall, 2003.
24. Xilinx. Fast simplex link (fsl) bus ip. http://www.xilinx.com/support/documentation/ip_documentation/fsl_v20.pdf.
25. Xilinx. Microblaze processor reference guide. http://www.xilinx.com/support/documentation/sw_manuals/mb_ref_guide.pdf.
26. P. Zhang, O. Elkeelany, and L. McDaniel. An implementation of secured smart grid ethernet communications using aes. In IEEE SoutheastCon 2010 (SoutheastCon), Proceedings of the, pages 394--397, march 2010.
27. X. Zhang and K. Parhi. High-speed vlsi architectures for the aes algorithm. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 12(9):957--967, sept. 2004.

Index Terms

• Hardware

  • Very large scale integration design

    • Application-specific VLSI designs

      • Application specific processors