Matthias Jung
Christian Weis
Karthik Chandrasekar
ABSTRACT
Three-dimensional stacked Wide I/O DRAMs have been proposed as a promising solution to overcome the pin-limited memory performance growth, the power vs. bandwidth dilemma and the Memory Wall. This new DRAM architecture and organisation requires a new generation of DRAM memory controllers.
In this paper, we present a new methodology using virtual platforms to model the backend of a 3D-DRAM memory subsystem (channel controller and Wide I/O DRAM) with special SystemC TLM2.0 phase extensions. This methodology enables us to explore the complete design space of memory controllers at the system level at very fast simulation speeds with precise timing accuracy. We show simulation speedups of up to 377x with a timing accuracy of 99% compared to an equivalent cycle and pin accurate SystemC based RTL simulation.
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Index Terms
- TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration
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