ABSTRACT
This paper describes architectural enhancements in the Altera Stratix-V" FPGA architecture, built on a 28nm TSMC process, together with the data supporting those choices. Among the key features are time borrowing flip-flops, a doubling of the number of flip-flops per LUT compared to previous Stratix architectures, a simplified embedded 20kb dual-port RAM block, and error correction that can correct up to 8 adjacent errors. Arithmetic performance is significantly improved using a fast adder with two levels of multi-bit skip. We also describe how the routing architecture and layout is optimized for the 28nm process to take advantage of a wider range of wire thicknesses offered on the different layers, and improvements in performance and routability are obtained without dramatic changes to the repeated floorplan of the logic plus routing fabric.
- V. Betz, J. Rose, and A. Marquardt, "Architecture and CAD for Deep-Submicron FPGAs", Kluwer Academic Publishers, 1999 Google ScholarDigital Library
- D. Lewis et al, "The Stratix-II" Routing and Logic Architecture", Proc FPGA 2005, pp. 14--20 Google ScholarDigital Library
- D. Lewis et al, "The Stratix" Routing and Logic Architecture", Proc FPGA 2003, pp. 12--20 Google ScholarDigital Library
- D. Lewis et al, "Architectural Enhancements in Stratix-III" and Stratix-IV"", Proc FPGA 2009, pp. 33--42 Google ScholarDigital Library
- N. Nedovic et al, "A Clock Skew Absorbing Flip-Flop", Proc ISSCC 2003, pp. 342--343Google Scholar
- V. G. Oklobdzija, "Clocking and clocked storage elements in a multi-gigahertz environment", IBM J. Res. Dev, Sept 2003, pp. 567--583 Google ScholarDigital Library
- B. Stackhouse et al., "A 65nm 2-Billion Transistor Quad-Core Itanium® Processor", IEEE JSSC, Jan 2009 pp. 18--31Google Scholar
- D. Wendel et al, "Power7®, a Highly Parallel, Scalable Multi-Core High End Server Processor", IEEE JSSC, Jan 2011, pp. 145--161Google Scholar
- M. Y. Hsiao, "A Class of Optimal minimum Odd-weight-column SEC-DED Codes", IBM J. Res. Dev., Jul 1970, pp. 395--401 Google ScholarDigital Library
- C. L. Chen and M. Y. Hsiao, "Error-correcting codes for semiconductor memory applications: A state-of-the-art review", IBM J. Res. Dev., Mar 1984, pp. 124--134 Google ScholarDigital Library
- R. Naseer and J. Draper, "DEC ECC Design to Improve Memory Reliability in Sub-100nm Technologies", IEEE Intl. Conf. on Electronics, Circuits, and Systems, 2008, pp. 586--589Google ScholarCross Ref
- R. Goodman and M. Sayano, "The Reliability of Semiconductor RAM Memories with On-Chip Error-Correction Coding", IEEE Trans. Information Theory, May 1991, pp. 884--896 Google ScholarCross Ref
- A. Dutta and N. Touba, "Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code", IEEE VLSI Test Symp., 2007, pp. 349--354 Google ScholarDigital Library
- D. Singh and S. Brown, "Constrained Clock Shifting for Field Programmable Gate Arrays", IEEE Intl. Symp. FPGAs 2002, Monterey, CA, Feb 2002, pp. 121--126. Google ScholarDigital Library
- B. Teng and J. Anderson, "Latch-Based Performance Optimization for FPGAs", Proc FPL 2011, pp. 53--64 Google ScholarDigital Library
- C.-Y. Yeh and M. Marek-Sadowska, "Skew-programmable clock design for FPGA and skew-aware placement", Proc. FPGA 2005, pp. 33--40 Google ScholarDigital Library
- X. Dong and G. Lemieux, "PRG: Period and glitch reduction via clock skew scheduling, delay padding, and GlitchLess", Proc. FPT 2009, pp. 88--95Google Scholar
- B. Teng and J.H. Anderson, "Latch-based performance optimization for FPGAs," accepted to appear IEEE Trans. VLSIGoogle Scholar
- S.Y. Wu et al., "A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM", Proc IEDM 2007, pp. 263--266Google Scholar
- H-C. Hsieh, et al, "Third-generation architecture boosts speed and density of field-programmable gate arrays," Custom Integrated Circuits Conference, 1990, pp.31.2.1--31.2.7Google Scholar
Index Terms
- Architectural enhancements in Stratix V™
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