Abstract
High-performance clock distribution has been a challenge for nearly three decades. During this time, clock synthesis tools and algorithms have strove to address a myriad of important issues helping designers to create faster, more reliable, and more power efficient chips. This work provides a complete discussion of the high-performance ASIC clock distribution using information gathered from both leading industrial clock designers and previous research publications. While many techniques are only briefly explained, the references summarize the most influential papers on a variety of topics for more in-depth investigation. This article also provides a thorough discussion of current issues in clock synthesis and concludes with insight into future research and design challenges for the community at large.
- Abdelhadi, A., Ginosar, R., Kolodny, A., and Friedman, E. G. 2010. Timing-driven variation-aware nonuniform clock mesh synthesis. In Proceedings of the Great Lakes Symposium on VLSI. 15--20. Google ScholarDigital Library
- Agarwal, A., Zolotov, V., and Blaauw, D. T. 2003. Statistical timing analysis using bounds and selective enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22, 9, 1243--1260. Google ScholarDigital Library
- Ajami, A., Banerjee, K., and Pedram, M. 2005. Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24, 6, 849--861. Google ScholarDigital Library
- Alpert, C., Kahng, A. B., Liu, B., Mandoiu, I., and Zelikovsky, A. 2001. Minimum-buffered routing of non-critical nets for slew rate and reliability control. In Proceedings of the International Conference on Computer-Aided Design. 408--415. Google ScholarDigital Library
- Bailey, D. and Benschneider, B. 1998. Clocking design and analysis for a 600-MHz Alpha microprocessor. J. Solid-State Circuits 33, 11, 1627--1633.Google ScholarCross Ref
- Bakoglu, H., Walker, J., and Meindl, J. 1986. A symmetric clock-distribution tree and optimized high-speed interconnections for reduced clock skew in ULSI and WSI circuits. In Proceedings of the International Conference on Computer Design. 118--122.Google Scholar
- Bansal, S., Rey, J. C., Yang, A., Jang, M.-S., Lu, L., Magarshack, P., Pol, M., and Radojcic, R. 2010. 3-D stacked die: Now or the future? In Proceedings of the Design Automation Conference. 298--299. Google ScholarDigital Library
- Benschneider, B. J., Black, A. J., et al. 1995. A 300-MHz 64-b quad-issue CMOS RISC microprocessor. J. Solid-State Circuits 30, 11, 1203--1214.Google ScholarCross Ref
- Blaauw, D., Chopra, K., Srivastava, A., and Scheffer, L. 2008. Statistical timing analysis: From basic principles to state of the art. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27, 4, 589--607. Google ScholarDigital Library
- Boese, K. and Kahng, A. 1992. Zero-skew clock routing trees with minimum wire length. In Proceedings of the ASIC Conference. 1--5.Google Scholar
- Burd, T. and Broderson, R. 2000. Design issues for dynamic voltage scaling. In Proceedings of the International Symposium on Low Power Electronic Design. 9--14. Google ScholarDigital Library
- Chakraborty, A., Duraisami, K., Sathanur, A., Sithambaram, P., Benini, L., Macii, A., Macii, E., and Poncino, M. 2006a. Dynamic thermal clock skew compensation using tunable delay buffers. In Proceedings of the International Symposium on Low Power Electronics and Design. 162--167. Google ScholarDigital Library
- Chakraborty, A., Ganesan, G., Rajaram, A., and Pan, D. Z. 2009. Analysis and optimization of NBTI induced clock skew in gated clock trees. In Proceedings of the Conference and Exhibition on Design, Automation and Test in Europe. 296--299. Google ScholarDigital Library
- Chakraborty, A. and Pan, D. Z. 2010. Skew management of NBTI impacted gated clock trees. In Proceedings of the International Symposium on Physical Design. 127--133. Google ScholarDigital Library
- Chakraborty, A., Sithambaram, P., Duraisami, K., Macii, A., Macii, E., and Poncino, M. 2006b. Thermal resilient bounded-skew clock tree optimization methodology. In Proceedings of the Conference and Exhibition on Design, Automation and Test in Europe. 832--837. Google ScholarDigital Library
- Chan, D. and Guthaus, M. R. 2010. Analysis of power supply induced jitter in actively de-skewed multicore systems. In Proceedings of the International Symposium on Quality Electronic Design.Google Scholar
- Chan, S., Restle, P., Shepard, K., James, N., and Franch, R. 2004. A 4.6GHz resonant global clock distribution network. In Proceedings of the International Solid-State Circuits Conference. 342--343.Google Scholar
- Chan, S. C., Shepard, K. L., and Restle, P. J. 2003. Design of resonant global clock distributions. In Proceedings of the International Conference on Computer Design. Google ScholarDigital Library
- Chang, C.-M., Huang, S.-H., Ho, Y.-K., Lin, J.-Z., Wang, H.-P., and Lu, Y.-S. 2008. Type-matching clock tree for zero skew clock gating. In Proceedings of the Design Automation Conference. 714--719. Google ScholarDigital Library
- Chang, H. and Sapatnekar, S. 2003. Statistical timing analysis considering spatial correlations using a single PERT-like traversal. In Proceedings of the International Conference on Computer-Aided Design. 621--625. Google ScholarDigital Library
- Chao, T.-H., Hsu, Y.-C., and Ho, J. 1992. Zero skew clock net routing. In Proceedings of the Design Automation Conference. 518--523. Google ScholarDigital Library
- Chao, W.-C. and Mak, W.-K. 2008. Low-power gated and buffered clock network construction. ACM Trans. Des. Autom. Electron. Syst. 13, 1, 1--20. Google ScholarDigital Library
- Chen, C.-P., Chen, Y.-P., and Wong, D. F. 1996. Optimal wire-sizing formula under the Elmore delay model. In Proceedings of the Design Automation Conference. 487--490. Google ScholarDigital Library
- Chen, Y. and Wong, D. 1996. An algorithm for zero-skew clock tree routing with buffer insertion. In Proceedings of the Conference and Exhibition on Design, Automation and Test in Europe. 230--236. Google ScholarDigital Library
- Chen, Y.-Y., Dong, C., and Chen, D. 2010. Clock tree synthesis under aggressive buffer insertion. In Proceedings of the Design Automation Conference. 86--89. Google ScholarDigital Library
- Chi, V. 1994. Salphasic distribution of clock signals for synchronous systems. IEEE Trans. Comput. 43, 5, 597--602. Google ScholarDigital Library
- Cho, J. and Sarrafzadeh, M. 1993. A buffer distribution algorithm for high-speed clock routing. In Proceedings of the Design Automation Conference. 537--543. Google ScholarDigital Library
- Cho, M., Ahmedtt, S., and Pan, D. 2005. TACO: temperature aware clock-tree optimization. In Proceedings of the International Conference on Computer-Aided Design. 582--587. Google ScholarDigital Library
- Cho, M., Pan, D., and Puri, R. 2010. Novel binary linear programming for high performance clock mesh synthesis. In Proceedings of the International Conference on Computer-Aided Design. 438--443. Google ScholarDigital Library
- Chu, C. and Pan, M. 2008. Handbook of Algorithms for Physical Design Automation. CRC Press, Chapter 42 and 43.Google Scholar
- Chung, J. and Cheng, C.-K. 1994. Skew sensitivity minimization of buffered clock tree. In Proceedings of the International Conference on Computer-Aided Design. 280--283. Google ScholarDigital Library
- Condley, W., Hu, X., and Guthaus, M. 2011. A methodology for local resonant clock synthesis using lc-assisted local clock buffers. In Proceedings of the International Conference on Computer-Aided Design. 503--506. Google ScholarDigital Library
- Condley, W., Hu, X., and Guthaus, M. R. 2010. Analysis of high-performance clock networks with RLC and transmission line effects. In Proceedings of the System-Level Interconnect Prediction Workshop. Google ScholarDigital Library
- Cong, J., He, L., Koh, C.-K., and Madden, P. H. 1996. Performance optimization of vlsi interconnect layout. Integration VLSI J. 21, 1&2, 1--94. Google ScholarDigital Library
- Cong, J. and Koh, C.-K. 1995. Minimum-cost bounded-skew clock routing. In Proceedings of the International Symposium on Circuits and Systems. 215--218.Google Scholar
- Dally, W. J. and Poulton, J. W. 1998. Digital Systems Engineering. Cambridge University Press. Google ScholarDigital Library
- Desai, M. P., Cvijetic, R., and Jensen, J. 1996. Sizing of clock distribution networks for high performance CPU chips. In Proceedings of the Design Automation Conference. 389--394. Google ScholarDigital Library
- Devgan, A. 1997. Efficient coupled noise estimation for on-chip interconnects. In Proceedings of the International Conference on Computer-Aided Design. 147--151. Google ScholarDigital Library
- Dobberpuhl, D., Witek, R., et al. 1992. A 200-MHz 64-b dual-issue CMOS microprocessor. J. Solid-State Circuits 27, 11, 1555--1567.Google ScholarCross Ref
- Dos Santos, C. L. 2010. Personal communication. Freescale Design Engineer.Google Scholar
- Drake, A., Nowka, K., Nguyen, T., Burns, J., and Brown, R. 2004. Resonant clocking using distributed parasitic capacitance. J. Solid-State Circuits 39, 9, 1520--1528.Google ScholarCross Ref
- Edahiro, M. 1992. Minimum path-length equi-distant routing. In Proceedings of the Asia-Pacific Conference on Circuits and Systems. 41--46.Google Scholar
- Edahiro, M. 1993a. A clustering-based optimization algorithm in zero-skew routings. In Proceedings of the Design Automation Conference. 612--616. Google ScholarDigital Library
- Edahiro, M. 1993b. Delay minimization for zero-skew routing. In Proceedings of the International Conference on Computer-Aided Design. 563--566.Google ScholarCross Ref
- Elmore, W. C. 1948. The transient response of damped linear networks. J. Appl. Physics 19, 55--63.Google ScholarCross Ref
- Chan, S. C., Restle, P. J., Bucelot, T. J., Liberty, J. S., Weitzel, S., Keaty, J. M., Flachs, B., Volant, R., Kapusta, P., and Zimmerman, J. S. 2009. A resonant global clock distribution for the cell broadband engine processor. IEEE J. Solid-State Circuits 44, 1.Google ScholarCross Ref
- Farrahi, A. H., Chen, C., Srivastava, A., Tellez, G., and Sarrafzadeh, M. 2001. Activity-driven clock design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20, 6, 705--714. Google ScholarDigital Library
- Fishburn, J. P. 1990. Clock skew optimization. IEEE Trans. Comput. 39, 7, 945--951. Google ScholarDigital Library
- Flach, G.,Wilke, G., Johann, M., and Reis, R. 2010a. A mesh-buffer displacement optimization strategy. In Proceedings of the International Symposium on VLSI. Google ScholarDigital Library
- Flach, G.,Wilke, G., Johann, M., and Reis, R. 2010b. A study on clock mesh size selection. In Proceedings of the Latin American Symposium on Circuits and Systems.Google Scholar
- Forzan, C. and Pandini, D. 2009. Statistical static timing analysis: A survey. Integration VLSI J. 42, 409--435. Google ScholarDigital Library
- Friedman, E. G. 2001. Clock distribution networks in synchronous digital integrated circuits. Proc. IEEE. 665--692.Google ScholarCross Ref
- Geannopoulos, G. and Dai, X. 1998. An adaptive digital deskewing circuit for distribution networks. In Proceedings of the International Solid-State Circuits Conference.Google Scholar
- Golden, M., Arekapudi, S., et al. 2006. A 2.6GHz dual-core 64bx86 microprocessor with DDR2 memory support. In Proceedings of the International Solid-State Circuits Conference. 104--105.Google ScholarCross Ref
- Gupta, P. and Heng, F.-L. 2004. Toward a systematic-variation aware timing methodology. In Proceedings of the Design Automation Conference. 321--326. Google ScholarDigital Library
- Guthaus, M., Hu, X., Wilke, G., Flache, G., and Reis, R. 2012. High-performance clock mesh optimization. ACM Trans. Des. Autom. Electronic Syst. 17, 3. Google ScholarDigital Library
- Guthaus, M. and Taskin, B. 2012. Embedded tutorial: High-performance, low-power resonant clocking. In Proceedings of the International Conference on Computer-Aided Design. Google ScholarDigital Library
- Guthaus, M. R. 2011. Distributed LC resonant clock tree synthesis. In Proceedings of the International Symposium on Circuits and Systems. 1215--1218.Google ScholarCross Ref
- Guthaus, M. R., Sylvester, D., and Brown, R. B. 2006. Clock buffer and wire sizing using sequential quadratic programming. In Proceedings of the Design Automation Conference. 1041--1046. Google ScholarDigital Library
- Guthaus, M. R., Sylvester, D., and Brown, R. B. 2008. Clock tree synthesis with data-path sensitivity matching. In Proceedings of the Asia and South Pacific Design Automation Conference. 498--503. Google ScholarDigital Library
- Guthaus, M. R., Wilke, G., and Reis, R. 2010. Non-uniform clock mesh optimization with linear programming buffer insertion. In Proceedings of the Design Automation Conference. 74--79. Google ScholarDigital Library
- Hashimoto, M., Yamamoto, T., and Onodera, H. 2005. Statistical analysis of clock skew variation in H-tree structure. In Proceedings of the International Symposium on Quality Electronic Design. 402--407. Google ScholarDigital Library
- Hathaway, D., Alvarez, J. P., and Belkbale, K. P. 1997. Network timing analysis between signals traversing a common circuit path. United States Patent 5,636,372.Google Scholar
- Heriz, V. M., Park, J.-H., Kemper, T., Kang, S.-M., and Shakouri, A. 2007. Method of images for the fast calculation of temperature distributions in packaged VLSI chips. In Proceedings of the 13th International Workshop on Thermal Investigation of ICs and Systems. 18--25.Google Scholar
- Hu, X., Condley, W., and Guthaus, M. 2012. Library-aware resonant clock synthesis. In Proceedings of the Design Automation Conference. 145--150. Google ScholarDigital Library
- Hu, X. and Guthaus, M. 2011. Distributed resonant clock grid synthesis (ROCKS). In Proceedings of the Design Automation Conference. 516--521. Google ScholarDigital Library
- Hu, X. and Guthaus, M. 2012. Distributed LC resonant clock grid synthesis. IEEE Trans. Circuits Syst. Regul. Pap.Google ScholarCross Ref
- Huang, D. J.-H., Kahng, A. B., and Tsao, C.-W. A. 1995. On the bounded-skew clock and steiner routing problems. In Proceedings of the Design Automation Conference. 508--513. Google ScholarDigital Library
- Im, S., Srivastava, N., Banerjee, K., and Goodson, K. E. 2005. Scaling analysis of multilevel interconnect temperatures for high performance ICs. IEEE Trans. Electron Devices 52, 12, 2710--2719.Google ScholarCross Ref
- Jackson, M. A. B., Srinivasan, A., and Kuh, E. S. 1990. Clock routing for high performance ICs. In Proceedings of the Design Automation Conference. 573--579. Google ScholarDigital Library
- Kahng, A. B., Cong, J., and Robins, G. 1991. High-performance clock routing based on recursive geometric matching. In Proceedings of the Design Automation Conference. 322--327. Google ScholarDigital Library
- Kapoor, A., Jayakumar, N., and Khatri, S. P. 2004. A novel clock distribution and dynamic de-skewing methodology. In Proceedings of the International Conference on Computer-Aided Design. 626--631. Google ScholarDigital Library
- Kay, R. and Pileggi, L. T. 1998. EWA: Efficient wiring-sizing algorithm for signal nets and clock nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17, 1, 40--49. Google ScholarDigital Library
- Kim, S.-D., Wada, H., and Woo, J. C. S. 2004. TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling. IEEE Trans. Semicond. Manuf. 17, 2, 192--200.Google ScholarCross Ref
- Kourtev, I. S. and Friedman, E. G. 1999. A quadratic programming approach to clock skew scheduling for reduced sensitivity to process parameter variations. In Proceedings of the International ASIC/SOC Conference. 210--215.Google Scholar
- Kozhaya, J., Restle, P., and Qian, H. 2011. Myth busters: Microprocessor clocking is from Mars, ASIC's clocking is from Venus? In Proceedings of the International Conference on Computer-Aided Design. 271--275. Google ScholarDigital Library
- Kurd, N., Barkatullah, J., Dizon, R., Fletcher, T., and Madland, P. 2001. Multi-GHz clocking scheme for Intel Pentium 4 microprocessor. In Proceedings of the International Solid-State Circuits Conference. 404--405.Google Scholar
- Lee, D. and Markov, I. 2010. Contango: Integrated optimization of SoC clock networks. In Proceedings of the Conference and Exhibition on Design, Automation and Test in Europe. 1468--1473. Google ScholarDigital Library
- Lee, D.-J., Kim, M.-C., and Markov, I. L. 2010. Low-power clock trees for CPUs. In Proceedings of the International Conference on Computer-Aided Design. 444--451. Google ScholarDigital Library
- Li, R., Zhou, D., Liu, J., and Zeng, X. 2003. Power-optimal simultaneous buffer insertion/sizing and wire sizing. In Proceedings of the International Conference on Computer-Aided Design. 581. Google ScholarDigital Library
- Liu, I.-M., Chou, T.-L., Aziz, A., and Wong, D. F. 2000. Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. In Proceedings of the International Symposium on Physical Design. 33--38. Google ScholarDigital Library
- Liu, W.-H., Li, Y.-L., and Chen, H.-C. 2010. Minimizing clock latency range in robust clock tree synthesis. In Proceedings of the Asia and South Pacific Design Automation Conference. 389--394. Google ScholarDigital Library
- Long, J., Ku, J. C., Memik, S., and Ismail, Y. 2007. A self-adjusting clock tree architecture to cope with temperature variations. In Proceedings of the International Conference on Computer-Aided Design. 75--82. Google ScholarDigital Library
- Lu, B., Hu, J., Ellis, G., and Su, H. 2003. Process variation aware clock tree routing. In Proceedings of the International Symposium on Physical Design. 174--181. Google ScholarDigital Library
- Markov, I. and Lee, D.-J. 2011. Algorithmic tuning of clock trees and derived non-tree structures. In Proceedings of the IEEE International Conference on Computer-Aided Design. 279--282. Google ScholarDigital Library
- Mekala, V. R., Liu, Y., Ye, X., Hu, J., and Li, P. 2010. Accurate clock mesh sizing via sequential quadratic programming. In Proceedings of the International Symposium on Physical Design. 135--142. Google ScholarDigital Library
- Menezes, N., Baldick, R., and Pileggi, L. 1995. A sequential quadratic programming approach to concurrent gate and wire sizing. In Proceedings of the International Conference on Computer-Aided Design. 144--151. Google ScholarDigital Library
- Mesa-Martinez, F., Ardestani, E., and Renau, J. 2010. Characterizing processor thermal behavior. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems. Google ScholarDigital Library
- Minz, J., Zhao, X., and Lim, S. K. 2008. Buffered clock tree synthesis for 3D ICs under thermal variations. In Proceedings of the Asia and South Pacific Design Automation Conference. 504--509. Google ScholarDigital Library
- Mittal, T. and Koh, C.-K. 2011. Cross link insertion for improving tolerance to variations in clock network synthesis. In Proceedings of the International Symposium on Physical Design. 29--36. Google ScholarDigital Library
- Nassif, S. R. 2001. Modeling and forecasting of manufacturing variations (embedded tutorial). In Proceedings of the Asia and South Pacific Design Automation Conference. 145--150. Google ScholarDigital Library
- Neves, J. L. and Friedman, E. G. 1996. Optimal clock skew scheduling tolerant to process variations. In Proceedings of the Design Automation Conference. 623--629. Google ScholarDigital Library
- Nowka, K. J. Carpenter, G. D., MacDonald, E. W., Ngo, H. C., Brock, B. C., Ishii, K. I., Nguyen, T. Y., and Burns, J. L. 2002. A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling. J. Solid State Circuits 37, 11, 1441--1447.Google ScholarCross Ref
- Oh, J. and Pedram, M. 1998. Gated clock routing minimizing the switched capacitance. In Proceedings of the Conference and Exhibition on Design, Automation and Test in Europe. 692--697. Google ScholarDigital Library
- O'Mahony, F., Yue, C., Horowitz, M., and Wong, S. 2003. Design of a 10GHz clock distribution network using coupled standing-wave oscillators. In Proceedings of the Design Automation Conference. 682--687. Google ScholarDigital Library
- Pelgrom, M., Duinmaijer, A., and Welbers, A. 1989. Matching properties of MOS transistors. J. Solid State Circuits 24, 5, 1433--1439.Google ScholarCross Ref
- Pullela, S., Menezes, N., and Pileggi, L. 1996. Post-processing of clock trees via wiresizing and buffering for robust design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.15, 6, 691--701. Google ScholarDigital Library
- Pullela, S., Menezes, N., and Pillage, L. T. 1993. Reliable non-zero skew clock trees using wire width optimization. In Proceedings of the Design Automation Conference. 165--170. Google ScholarDigital Library
- Rajaram, A., Damodaran, R., and Rajagopal, A. 2008. Practical clock tree robustness signoff metrics. In Proceedings of the International Symposium on Quality Electronic Design. 676--679. Google ScholarDigital Library
- Rajaram, A., Hu, J., and Mahapatra, R. 2004. Reducing clock skew variability via cross links. In Proceedings of the Design Automation Conference. 18--23. Google ScholarDigital Library
- Rajaram, A. and Pan, D. Z. 2008. Meshworks: an efficient framework for planning, synthesis and optimization of clock mesh networks. In Proceedings of the Asia and South Pacific Design Automation Conference. 250--257. Google ScholarDigital Library
- Rao, R. R., Blaauw, D., Sylvester, D., Alpert, C. J., and Nassif, S. 2005. An efficient surface-based low-power buffer insertion algorithm. In Proceedings of the International Symposium on Physical Design. 86--93. Google ScholarDigital Library
- Restle, P., Carter, C., Eckhardt, J., Krauter, B., McCredie, B., Jenkins, K., Weger, A., and Mule, A. 2002. The clock distribution of the POWER4 microprocessor. In Proceedings of the International Solid-State Circuits Conference. 144--145.Google Scholar
- Rosenfeld, J. and Friedman, E. 2006. Design methodology for global resonant h-tree clock distribution networks. In Proceedings of the International Symposium on Circuits and Systems. Google ScholarDigital Library
- Rusu, S., Tam, S., Muljono, H., Ayers, D., and Chang, J. 2006. A dual-core multi-threaded Xeon processor with 16MB L3 cache. In Proceedings of the International Solid-State Circuits Conference. 102--103.Google Scholar
- Saaied, H., Al-Khalili, D., Al-Halili, A. J., and Nekili, M. 2005. Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24, 10, 1637--1643. Google ScholarDigital Library
- Sapatnekar, S. 2004. Timing. Springer. Google ScholarDigital Library
- Sathe, V., Arekapudi, S., Ouyang, C., Papaefthymiou, M., Ishii, A., and Naffziger, S. 2012. Resonant clock design for a power-efficient high-volume x86-64 microprocessor. In Proceedings of the International Solid State Circuits Conference. 68--70.Google Scholar
- Sathe, V., Kao, J., and Papaefthymiou, M. 2007. RF2: A 1GHz FIR filter with distributed resonant clock generator. In Proceedings of the IEEE Symposium on VLSI Circuits. 44--45.Google Scholar
- Sekar, D. 2005. Clock trees: differential or single ended? In Proceedings of the International Symposium on Quality Electronic Design. 548--553. Google ScholarDigital Library
- Shelar, R. S. 2009. An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors. In Proceedings of the International Symposium on Physical Design. 141--148. Google ScholarDigital Library
- Shih, X.-W. and Chang, Y.-W. 2010. Fast timing-model independent buffered clock-tree synthesis. In Proceedings of the Design Automation Conference. 80--85. Google ScholarDigital Library
- Shih, X.-W., Lee, H.-C., Ho, K.-H., and Chang, Y.-W. 2010. High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees. In Proceedings of the International Conference on Computer-Aided Design. 452--457. Google ScholarDigital Library
- Skinner, H., Hu, X., and Guthaus, M. R. 2012. Harmonic resonant clocking. In Proceedings of the International Conference on Very Large Scale Integration.Google Scholar
- Steinhogl, W., Schindler, G., Steinlesberger, G., Traving, M., and Engelhardt, M. 2004. Impact of line edge roughness on the resistivity of nanometer-scale interconnects. Microelectron. Eng. 76, 126--130.Google ScholarDigital Library
- Stine, B. E., Boning, D. S., et al. 1998. The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes. IEEE Trans. Electron Devices 45, 3, 665--679.Google ScholarCross Ref
- Sze, C. 2010a. Personal communication. IBM Austin Research Lab, Austin, TX.Google Scholar
- Sze, C. N. 2010b. ISPD 2010 high performance clock network synthesis contest. In Proceedings of the International Symposium on Physical Design. Google ScholarDigital Library
- Sze, C. N., Restle, P., Nam, G.-J., and Alpert, C. J. 2009. Clocking and the ISPD'09 clock synthesis contest. In Proceedings of the International Symposium on Physical Design. 149--150. Google ScholarDigital Library
- Tam, S., Leung, J., Limaye, R., Choy, S., Vora, S., and Adachi, M. 2006. Clock generation and distribution of a dual-core Xeon processor with 16MB L3 cache. In Proceedings of the International Solid-State Circuits Conference. 382--383.Google Scholar
- Taskin, B., Demaio, J., Farell, O., Hazeltine, M., and Ketner, R. 2009. Custom topology rotary clock router with tree subnetworks. ACM Trans. Des. Autom. Electron. Syst. 14, 3. Google ScholarDigital Library
- Tellez, G. E. and Sarrafzadeh, M. 1997. Minimal buffer insertion in clock trees with skew and slew rate constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16, 4, 333--342. Google ScholarDigital Library
- Teodorescu, T. 2010. Personal communication. ATI Radeon 5870 Clock Designer, Sunnyvale, CA.Google Scholar
- Thomson, M. G.-R., Restle, P. J., and James, N. K. 2006. A 5GHz duty-cycle correcting clock distribution network for the POWER6 microprocessor. In Proceedings of the International Solid-State Circuits Conference. 1522--1529.Google Scholar
- Tolbert, J., Zhao, X., Lim, S.-K., and Mukhopadhyay, S. 2009. Slew-aware clock tree design for reliable subthreshold circuits. In Proceedings of the International Symposium on Low Power Electronics and Design. 15--20. Google ScholarDigital Library
- Tsai, J.-L., Baik, D.-H., Chen, C. C., and Saluja, K. K. 2004. A yield improvement methodology using pre- and post-silicon statistical clock scheduling. In Proceedings of the International Conference on Computer-Aided Design. 611--618. Google ScholarDigital Library
- Tsai, J.-L., Chen, T.-H., and Chen, C. C. 2004. Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23, 4, 565--573. Google ScholarDigital Library
- Tsai, J.-L., Zhang, L., and Chen, C. C.-P. 2005. Statistical timing analysis driven post-silicon tunable clock-tree synthesis. In Proceedings of the International Conference on Computer-Aided Design. 575--581. Google ScholarDigital Library
- Tsao, C.-W. and Koh, C.-K. 2000. UST/DME: A clock tree router for general slew constraints. In Proceedings of the IEEE International Conference on Computer-Aided Design. 400--405. Google ScholarDigital Library
- Tsao, C.-W. and Koh, C.-K. 2002. UST/DME: a clock tree router for general slew constraints. ACM Trans. Des. Autom. Electron.Syst. 7, 3, 359--379. Google ScholarDigital Library
- Tsay, R.-S. 1991. Exact zero skew. In Proceedings of the International Conference on Computer-Aided Design. 336--339.Google ScholarCross Ref
- Van Ginneken, L. P. P. P. 1990. Buffer placement in distributed RC-tree networks for minimal Elmore delay. In Proceedings of the International Symposium on Circuits and Systems. 865--868.Google ScholarCross Ref
- Vandenberghe, L., Boyd, S., and El Gamal, A. 1997. Optimal wire and transistor sizing for circuits with non-tree topology. In Proceedings of the International Conference on Computer-Aided Design. 252--259. Google ScholarDigital Library
- Venkataraman, G., Jayakumar, N., Hu, J., Li, P., Khatri, S., Rajaram, A., McGuinness, P., and Alpert, C. J. 2005a. Practical techniques to reduce skew and its variations in buffered clock networks. In Proceedings of the International Conference on Computer-Aided Design. 592--596. Google ScholarDigital Library
- Venkataraman, G., Sze, C. N., and Hu, J. 2005b. Skew scheduling and clock routing for improved tolerance to process variations. In Proceedings of the Asia and South Pacific Design Automation Conference. 594--599. Google ScholarDigital Library
- Venkataraman, G., Zhuo, F., Hu, J., and Li, P. 2006. Combinatorial algorithms for fast clock mesh optimization. In Proceedings of the International Conference on Computer-Aided Design. 563--567. Google ScholarDigital Library
- Visweswariah, C. 2003. Death, taxes and failing chips. In Proceedings of the Design Automation Conference. 343--347. Google ScholarDigital Library
- Visweswariah, C., Ravindran, K., Kalafala, K., Walker, S. G., and Narayan, S. 2004. First-order incremental block-based statistical timing analysis. In Proceedings of the Design Automation Conference. 331--336. Google ScholarDigital Library
- Vittal, A. and Marek-Sadowska, M. 1995. Power optimal buffered clock tree design. In Proceedings of the Design Automation Conference. 497--502. Google ScholarDigital Library
- Wang, K. and Marek-Sadowska, M. 2004. Buffer sizing for clock power minimization subject to general skew constraints. In Proceedings of the Design Automation Conference. 159--164. Google ScholarDigital Library
- Wang, T.-Y. and Chen, C. C.-P. 2001. Thermal-ADI: A linear-time chip-level dynamic thermal simulation algorithm based on alternating-direction-implicit (adi) method. In Proceedings of the International Symposium on Physical Design. 238--243. Google ScholarDigital Library
- Wilke, G., Fonseca, R., Mezzomo, C., and Reis, R. 2008. A novel scheme to reduce short-circuit power in mesh-based clock architectures. In Proceedings of the Symposium on Integrated Circuits and System Design. 117--122. Google ScholarDigital Library
- Wood, J., Edwards, T. C., and Lipa, S. 2001. Rotary traveling-wave oscillator arrays: A new clock technology. J. Solid-State Circuits 36, 11, 1654--1664.Google ScholarCross Ref
- Wood, J., Tekin, A., Dave, A., and Pedrotti, K. 2008. Giga-hertz rate single slope conversion technique with 512-phase rtwo. Analog Integrated Circuits and Signal Processing 55, 139--148. Google ScholarDigital Library
- Xanthopoulos, T. 2009. Clocking in Modern VLSI Systems. Springer. Google ScholarDigital Library
- Xanthopoulos, T., Bailey, D. W., Gangwar, A. K., Gowan, M. K., Jain, A. K., and Prewitt, B. K. 2001. The design and analysis of the clock distribution network for a 1.2GHz alpha microprocessor. In Proceedings of the International Solid State Circuits Conference. 402--403.Google Scholar
- Xi, J. G. and Dai, W. W.-M. 1995. Buffer insertion and sizing under process variation for low power clock distribution. In Proceedings of the Design Automation Conference. 491--496. Google ScholarDigital Library
- Xiao, L., Xiao, Z., Qian, Z., Jiang, Y, Huang, T., Tian, H., and Young, E. 2010. Local clock skew minimization using blockage-aware mixed tree-mesh clock network. In Proceedings of the International Conference on Computer-Aided Design. 458--462. Google ScholarDigital Library
- Yu, H., Hu, Y., Liu, C., and He, L. 2007. Minimal skew clock embedding considering time variant temperature gradient. In Proceedings of the International Symposium on Physical Design. 173--180. Google ScholarDigital Library
- Yu, Z. and Liu, X. 2009. Implementing multiphase resonant clocking on a finite-impulse response filter. IEEE Trans. VLSI Syst. 17, 11, 1593--1601. Google ScholarDigital Library
- Zejda, J. and Frain, P. 2002. General framework for removal of clock network pessimism. In Proceedings of the International Conference on Computer-Aided Design. 632--639. Google ScholarDigital Library
- Zeng, X., Zhou, D., and Li, W. 1999. Buffer insertion for clock delay and skew minimization. In Proceedings of the International Symposium on Physical Design. 36--41. Google ScholarDigital Library
- Zhan, Y. and Sapatnekar, S. S. 2007. High-efficiency green function-based thermal simulation algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26, 9, 1661--1675. Google ScholarDigital Library
- Zhao, W. and Cao, Y. 2006a. New generation of predictive technology model for sub-45 nm early design exploration. IEEE Trans. Electron. Devices 53, 11, 2816--2823.Google ScholarCross Ref
- Zhao, W. and Cao, Y. 2006b. New generation of predictive technology model for sub-45nm design exploration. In Proceedings of the International Symposium on Quality Electronic Design. 585--590. Google ScholarDigital Library
- Zhu, Q. 2010. High-Speed Clock Network Design. Springer. Google ScholarDigital Library
- Zhu, Q. and Zhang, M. 2001. Low-voltage swing clock distribution schemes. In Proceedings of the International Symposium on Circuits and Systems. 418--421.Google Scholar
Index Terms
Revisiting automated physical synthesis of high-performance clock networks
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