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Revisiting automated physical synthesis of high-performance clock networks

Published:11 April 2013Publication History
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Abstract

High-performance clock distribution has been a challenge for nearly three decades. During this time, clock synthesis tools and algorithms have strove to address a myriad of important issues helping designers to create faster, more reliable, and more power efficient chips. This work provides a complete discussion of the high-performance ASIC clock distribution using information gathered from both leading industrial clock designers and previous research publications. While many techniques are only briefly explained, the references summarize the most influential papers on a variety of topics for more in-depth investigation. This article also provides a thorough discussion of current issues in clock synthesis and concludes with insight into future research and design challenges for the community at large.

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  1. Revisiting automated physical synthesis of high-performance clock networks

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      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 18, Issue 2
      March 2013
      429 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/2442087
      Issue’s Table of Contents

      Copyright © 2013 ACM

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      Publication History

      • Published: 11 April 2013
      • Accepted: 1 September 2012
      • Revised: 1 November 2011
      • Received: 1 June 2011
      Published in todaes Volume 18, Issue 2

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