research-article

A hard real-time capable multi-core SMT processor

Authors:

Marco Paolieri,

Stefan Metzlaff,

Eduardo Quiñones,

Francisco J. CazorlaAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 12, Issue 3

Article No.: 79, Pages 1 - 26

https://doi.org/10.1145/2442116.2442129

Published: 08 April 2013 Publication History

Abstract

Hard real-time applications in safety critical domains require high performance and time analyzability. Multi-core processors are an answer to these demands, however task interferences make multi-cores more difficult to analyze from a worst-case execution time point of view than single-core processors. We propose a multi-core SMT processor that ensures a bounded maximum delay a task can suffer due to inter-task interferences. Multiple hard real-time tasks can be executed on different cores together with additional non real-time tasks. Our evaluation shows that the proposed MERASA multi-core provides predictability for hard real-time tasks and also high performance for non hard real-time tasks.

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Serrano-Cases AMezzetti EAbella JCazorla F(2024)Achieving Flexible Performance Isolation on the AMD Xilinx Zynq UltraScale+2024 27th Euromicro Conference on Digital System Design (DSD)10.1109/DSD64264.2024.00045(282-290)Online publication date: 28-Aug-2024
https://doi.org/10.1109/DSD64264.2024.00045
Jellum ELin SDonovan PJerad CWang ELohstroh MLee ESchoeberl M(2023)InterPRET: a Time-predictable Multicore ProcessorProceedings of Cyber-Physical Systems and Internet of Things Week 202310.1145/3576914.3587497(331-336)Online publication date: 9-May-2023
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Cerrolaza JObermaisser RAbella JCazorla FGrüttner KAgirre IAhmadian HAllende I(2020)Multi-core Devices for Safety-critical SystemsACM Computing Surveys10.1145/339866553:4(1-38)Online publication date: 3-Aug-2020
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Index Terms

A hard real-time capable multi-core SMT processor
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 12, Issue 3

March 2013

463 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/2442116

Issue’s Table of Contents

Copyright © 2013 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 08 April 2013

Accepted: 01 October 2011

Revised: 01 October 2011

Received: 01 June 2011

Published in TECS Volume 12, Issue 3

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Funding Sources

The Ministry of Science and Technology of Spain has been partially funding this work under contract TIN-2007-60625
Ministerio de Ciencia e Innovación
Seventh Framework Programme
European Social Fund

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Cited By

Serrano-Cases AMezzetti EAbella JCazorla F(2024)Achieving Flexible Performance Isolation on the AMD Xilinx Zynq UltraScale+2024 27th Euromicro Conference on Digital System Design (DSD)10.1109/DSD64264.2024.00045(282-290)Online publication date: 28-Aug-2024
https://doi.org/10.1109/DSD64264.2024.00045
Jellum ELin SDonovan PJerad CWang ELohstroh MLee ESchoeberl M(2023)InterPRET: a Time-predictable Multicore ProcessorProceedings of Cyber-Physical Systems and Internet of Things Week 202310.1145/3576914.3587497(331-336)Online publication date: 9-May-2023
https://dl.acm.org/doi/10.1145/3576914.3587497
Cerrolaza JObermaisser RAbella JCazorla FGrüttner KAgirre IAhmadian HAllende I(2020)Multi-core Devices for Safety-critical SystemsACM Computing Surveys10.1145/339866553:4(1-38)Online publication date: 3-Aug-2020
https://dl.acm.org/doi/10.1145/3398665
Roozkhosh SMancuso R(2020)The Potential of Programmable Logic in the Middle: Cache Bleaching2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS48715.2020.00006(296-309)Online publication date: Apr-2020
https://doi.org/10.1109/RTAS48715.2020.00006
Maiza CRihani HRivas JGoossens JAltmeyer SDavis R(2019)A Survey of Timing Verification Techniques for Multi-Core Real-Time SystemsACM Computing Surveys10.1145/332321252:3(1-38)Online publication date: 18-Jun-2019
https://dl.acm.org/doi/10.1145/3323212
van Wagensveld RWägemann TMader RTavakoli Kolagari RMargull U(2019)Evaluation and modeling of the supercore parallelization pattern in automotive real-time systemsParallel Computing10.1016/j.parco.2018.12.00481(122-130)Online publication date: Jan-2019
https://doi.org/10.1016/j.parco.2018.12.004
van Wagensveld RWägemann THehenkamp NKolagari RMargull UMader R(2018)Intra-Task Parallelism in Automotive Real-Time SystemsProceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores10.1145/3178442.3178449(61-70)Online publication date: 24-Feb-2018
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Hoozemans Jvan Straten JWong S(2018)Increasing resource utilization in mixed-criticality systems using a polymorphic VLIW processorJournal of Systems Architecture10.1016/j.sysarc.2018.01.00384(2-11)Online publication date: Mar-2018
https://doi.org/10.1016/j.sysarc.2018.01.003
Poursafaei FBazzaz MKafshdooz MEjlali A(2018)Slack clustering for scheduling frame-based tasks on multicore embedded systemsMicroelectronics Journal10.1016/j.mejo.2018.09.00281(144-153)Online publication date: Nov-2018
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Doyle NMatthews EHolland GFedorova AShannon L(2017)Performance impacts and limitations of hardware memory access trace collectionProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130496(506-511)Online publication date: 27-Mar-2017
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