research-article

Creation of ESL power models for communication architectures using automatic calibration

Authors:

Stefan Schürmans,

Diandian Zhang,

Rainer Leupers,

Lun WangAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 58, Pages 1 - 58

https://doi.org/10.1145/2463209.2488804

Published: 29 May 2013 Publication History

Abstract

Power consumption is an important factor in chip design. The fundamental design decisions drawn during early design space exploration at electronic system level (ESL) have a large impact on the power consumption. This requires to estimate power already at ESL, which is usually not possible using standard ESL component libraries due to missing power models. This work proposes a methodology that allows extension of ESL models with a power model and to automatically calibrate it to match a power trace obtained by gate-level simulation or measurements. Two case studies show that the methodology is suitable even for complex communication architectures.

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Cited By

Kogel T(2024)Virtual Prototyping of Processor-Based PlatformsHandbook of Computer Architecture10.1007/978-981-97-9314-3_44(947-987)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-981-97-9314-3_44
Herdt VGroße DDrechsler RHerdt VGroße DDrechsler R(2023)Validierung von Firmware-basiertem Power Management mit virtuellen PrototypenVerbessertes virtuelles Prototyping10.1007/978-3-031-18174-0_7(189-219)Online publication date: 1-Jan-2023
https://doi.org/10.1007/978-3-031-18174-0_7
Kogel T(2022)Virtual Prototyping of Processor-Based PlatformsHandbook of Computer Architecture10.1007/978-981-15-6401-7_44-1(1-41)Online publication date: 27-Jan-2022
https://doi.org/10.1007/978-981-15-6401-7_44-1
Show More Cited By

Index Terms

Creation of ESL power models for communication architectures using automatic calibration
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies
2. Hardware
  1. Hardware validation

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cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 May 2013

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DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

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Cited By

Kogel T(2024)Virtual Prototyping of Processor-Based PlatformsHandbook of Computer Architecture10.1007/978-981-97-9314-3_44(947-987)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-981-97-9314-3_44
Herdt VGroße DDrechsler RHerdt VGroße DDrechsler R(2023)Validierung von Firmware-basiertem Power Management mit virtuellen PrototypenVerbessertes virtuelles Prototyping10.1007/978-3-031-18174-0_7(189-219)Online publication date: 1-Jan-2023
https://doi.org/10.1007/978-3-031-18174-0_7
Kogel T(2022)Virtual Prototyping of Processor-Based PlatformsHandbook of Computer Architecture10.1007/978-981-15-6401-7_44-1(1-41)Online publication date: 27-Jan-2022
https://doi.org/10.1007/978-981-15-6401-7_44-1
Galicia MBanaGozar ASturm KStaudigl FStuijk SCorporaal HLeupers R(2021)NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators2021 IEEE 34th International System-on-Chip Conference (SOCC)10.1109/SOCC52499.2021.9739585(236-241)Online publication date: 14-Sep-2021
https://doi.org/10.1109/SOCC52499.2021.9739585
Herdt VLe HGroße DDrechsler RShibuya T(2019)Maximizing power state cross coverage in firmware-based power managementProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287631(335-340)Online publication date: 21-Jan-2019
https://dl.acm.org/doi/10.1145/3287624.3287631
Onnebrink GLeupers RAscheid GChillet D(2018)ESL Black Box Power EstimationProceedings of the Rapido'18 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/3180665.3180667(1-6)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.1145/3180665.3180667
Lee DGerstlauer A(2018)Learning-Based, Fine-Grain Power Modeling of System-Level Hardware IPsACM Transactions on Design Automation of Electronic Systems10.1145/317786523:3(1-25)Online publication date: 23-Feb-2018
https://dl.acm.org/doi/10.1145/3177865
Herdt VLe HGroße DDrechsler R(2018)Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random ApproachLanguages, Design Methods, and Tools for Electronic System Design10.1007/978-3-030-02215-0_2(25-44)Online publication date: 20-Dec-2018
https://doi.org/10.1007/978-3-030-02215-0_2
Schuermans SLeupers RSchuermans SLeupers R(2018)Network on Chip ExperimentsPower Estimation on Electronic System Level using Linear Power Models10.1007/978-3-030-01875-7_5(97-140)Online publication date: 15-Dec-2018
https://doi.org/10.1007/978-3-030-01875-7_5
Deng CLiu LLiu YYin SWei S(2017)PMCC: Fast and Accurate System-Level Power Modeling for Processors on Heterogeneous SoCIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2016.261593064:5(540-544)Online publication date: May-2017
https://doi.org/10.1109/TCSII.2016.2615930
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